From 52912c632972775008cc6215b70ba465dd51ed46 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 9 Jun 2008 21:25:10 -0400 Subject: [PATCH] Convert repository to git from svn. - Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines --- .cvsignore => .gitignore | 2 +- Changes | 2 - Makefile.in | 25 +++++----- TODO | 17 ++++--- bin/verilator | 4 +- bin/verilator_difftree | 4 +- bin/verilator_includer | 1 - bin/verilator_profcfunc | 4 +- configure.ac | 2 - include/{.cvsignore => .gitignore} | 0 include/verilated.cpp | 12 ++--- include/verilated.h | 42 ++++++++--------- include/verilated.mk.in | 8 ++-- include/verilated.v | 6 +-- include/verilatedos.h | 14 +++--- install-sh | 2 +- mkinstalldirs | 2 - nodist/bisonreader | 7 ++- nodist/dot_importer | 4 +- nodist/dot_pruner | 4 +- nodist/invoke_ncverilog | 1 - nodist/leakchecking.txt | 4 ++ nodist/vtree_importer | 6 +-- readme.texi | 17 ++++--- src/{.cvsignore => .gitignore} | 0 src/Makefile.in | 6 +-- src/Makefile_obj.in | 2 +- src/V3Active.cpp | 3 +- src/V3Active.h | 2 +- src/V3ActiveTop.cpp | 3 +- src/V3ActiveTop.h | 2 +- src/V3Assert.cpp | 3 +- src/V3Assert.h | 2 +- src/V3AssertPre.cpp | 1 - src/V3AssertPre.h | 2 +- src/V3Ast.cpp | 17 ++++--- src/V3Ast.h | 4 +- src/V3AstNodes.cpp | 1 - src/V3AstNodes.h | 10 ++-- src/V3Begin.cpp | 3 +- src/V3Begin.h | 2 +- src/V3Branch.cpp | 1 - src/V3Branch.h | 2 +- src/V3Broken.cpp | 3 +- src/V3Broken.h | 2 +- src/V3Case.cpp | 9 ++-- src/V3Case.h | 2 +- src/V3Cast.cpp | 5 +- src/V3Cast.h | 2 +- src/V3Changed.cpp | 3 +- src/V3Changed.h | 2 +- src/V3Clean.cpp | 5 +- src/V3Clean.h | 2 +- src/V3Clock.cpp | 5 +- src/V3Clock.h | 2 +- src/V3Combine.cpp | 5 +- src/V3Combine.h | 2 +- src/V3Const.cpp | 11 ++--- src/V3Const.h | 2 +- src/V3Coverage.cpp | 5 +- src/V3Coverage.h | 2 +- src/V3Dead.cpp | 3 +- src/V3Dead.h | 2 +- src/V3Delayed.cpp | 13 +++--- src/V3Delayed.h | 2 +- src/V3Depth.cpp | 5 +- src/V3Depth.h | 2 +- src/V3DepthBlock.cpp | 3 +- src/V3DepthBlock.h | 2 +- src/V3Descope.cpp | 3 +- src/V3Descope.h | 2 +- src/V3EmitC.cpp | 15 +++--- src/V3EmitC.h | 2 +- src/V3EmitCBase.h | 2 +- src/V3EmitCInlines.cpp | 1 - src/V3EmitCSyms.cpp | 3 +- src/V3EmitMk.cpp | 1 - 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test_regress/t/t_order_comboclkloop.v | 1 - test_regress/t/t_order_comboloop.pl | 1 - test_regress/t/t_order_comboloop.v | 1 - test_regress/t/t_order_doubleloop.pl | 1 - test_regress/t/t_order_doubleloop.v | 1 - test_regress/t/t_order_multialways.pl | 1 - test_regress/t/t_order_multialways.v | 1 - test_regress/t/t_order_wireloop.pl | 1 - test_regress/t/t_order_wireloop.v | 1 - test_regress/t/t_param.pl | 1 - test_regress/t/t_param.v | 3 +- test_regress/t/t_param_concat.pl | 1 - test_regress/t/t_param_concat.v | 1 - test_regress/t/t_param_concat_bad.pl | 1 - test_regress/t/t_param_long.pl | 1 - test_regress/t/t_param_long.v | 1 - test_regress/t/t_param_named.pl | 1 - test_regress/t/t_param_named.v | 1 - test_regress/t/t_param_named_2.pl | 1 - test_regress/t/t_param_named_2.v | 1 - test_regress/t/t_param_repl.pl | 1 - test_regress/t/t_param_repl.v | 1 - test_regress/t/t_pp_display.pl | 1 - test_regress/t/t_pp_display.v | 1 - test_regress/t/t_pp_dupdef.pl | 1 - test_regress/t/t_pp_dupdef.v | 3 +- test_regress/t/t_pp_dupdef_bad.pl | 1 - test_regress/t/t_pp_lib.pl | 1 - test_regress/t/t_pp_lib.v | 1 - test_regress/t/t_pp_lib_inc.v | 1 - test_regress/t/t_pp_lib_library.v | 1 - test_regress/t/t_pp_misdef_bad.pl | 3 +- test_regress/t/t_pp_misdef_bad.v | 1 - test_regress/t/t_pp_pragmas.pl | 1 - test_regress/t/t_pp_pragmas.v | 1 - test_regress/t/t_preproc.pl | 1 - test_regress/t/t_preproc.v | 2 +- test_regress/t/t_preproc_dos.pl | 1 - test_regress/t/t_preproc_ifdef.pl | 1 - test_regress/t/t_preproc_ifdef.v | 1 - test_regress/t/t_preproc_kwd.pl | 1 - test_regress/t/t_preproc_kwd.v | 1 - test_regress/t/t_preproc_psl.v | 2 +- test_regress/t/t_preproc_psl_off.pl | 1 - test_regress/t/t_preproc_psl_on.pl | 1 - test_regress/t/t_psl_basic.pl | 1 - test_regress/t/t_psl_basic.v | 1 - test_regress/t/t_psl_basic_cover.pl | 1 - test_regress/t/t_psl_basic_off.pl | 1 - test_regress/t/t_select_bad_msb.pl | 1 - test_regress/t/t_select_bad_msb.v | 1 - test_regress/t/t_select_bad_range.pl | 1 - test_regress/t/t_select_bad_range.v | 1 - test_regress/t/t_select_index.pl | 1 - test_regress/t/t_select_index.v | 1 - test_regress/t/t_select_plus.pl | 1 - test_regress/t/t_select_plus.v | 3 +- test_regress/t/t_select_plusloop.pl | 1 - test_regress/t/t_select_plusloop.v | 5 +- test_regress/t/t_select_runtime_range.pl | 1 - test_regress/t/t_select_runtime_range.v | 1 - test_regress/t/t_select_set.pl | 1 - test_regress/t/t_select_set.v | 1 - test_regress/t/t_sys_file.pl | 1 - test_regress/t/t_sys_file.v | 1 - test_regress/t/t_sys_readmem.pl | 1 - test_regress/t/t_sys_readmem.v | 3 +- test_regress/t/t_sys_readmem_b.mem | 1 - test_regress/t/t_sys_readmem_b_8.mem | 1 - test_regress/t/t_sys_readmem_bad_addr.mem | 1 - test_regress/t/t_sys_readmem_bad_addr.pl | 1 - test_regress/t/t_sys_readmem_bad_addr.v | 1 - test_regress/t/t_sys_readmem_bad_digit.mem | 1 - test_regress/t/t_sys_readmem_bad_digit.pl | 1 - test_regress/t/t_sys_readmem_bad_digit.v | 1 - test_regress/t/t_sys_readmem_bad_end.mem | 1 - test_regress/t/t_sys_readmem_bad_end.pl | 1 - test_regress/t/t_sys_readmem_bad_end.v | 1 - test_regress/t/t_sys_readmem_bad_notfound.pl | 1 - test_regress/t/t_sys_readmem_bad_notfound.v | 1 - test_regress/t/t_sys_readmem_h.mem | 1 - test_regress/t/t_trace_ena.v | 1 - test_regress/t/t_trace_ena_cc.pl | 1 - test_regress/t/t_trace_ena_sc.pl | 1 - test_regress/t/t_trace_ena_sp.pl | 1 - test_regress/t/t_trace_off_cc.pl | 1 - test_regress/t/t_trace_off_sc.pl | 1 - test_regress/t/t_trace_off_sp.pl | 1 - test_regress/t/t_unopt_combo.pl | 1 - test_regress/t/t_unopt_combo.v | 3 +- test_regress/t/t_unopt_combo_bad.pl | 1 - test_regress/t/t_unopt_combo_isolate.pl | 1 - test_regress/t/t_unopt_converge.v | 1 - test_regress/t/t_unopt_converge_print_bad.pl | 1 - test_regress/t/t_unopt_converge_run_bad.pl | 1 - test_regress/t/t_unopt_converge_unopt_bad.pl | 1 - test_regress/t/t_unroll_signed.pl | 1 - test_regress/t/t_unroll_signed.v | 1 - test_regress/t/t_var_bad_hide.pl | 1 - test_regress/t/t_var_bad_hide.v | 1 - test_regress/t/t_var_bad_rsvd.pl | 1 - test_regress/t/t_var_bad_rsvd.v | 1 - test_regress/t/t_var_bad_sameas.pl | 1 - test_regress/t/t_var_bad_sameas.v | 1 - test_regress/t/t_var_dotted.v | 3 +- test_regress/t/t_var_dotted_inl0.pl | 1 - test_regress/t/t_var_dotted_inl1.pl | 1 - test_regress/t/t_var_dotted_inl2.pl | 1 - test_regress/t/t_var_in_assign_bad.pl | 1 - test_regress/t/t_var_in_assign_bad.v | 1 - test_regress/t/t_var_init.pl | 1 - test_regress/t/t_var_init.v | 1 - test_regress/t/t_var_life.pl | 1 - test_regress/t/t_var_life.v | 1 - test_regress/t/t_var_local.pl | 1 - test_regress/t/t_var_local.v | 1 - test_regress/t/t_var_outoforder.pl | 1 - test_regress/t/t_var_outoforder.v | 1 - test_regress/t/t_var_pins_cc.pl | 1 - test_regress/t/t_var_pins_sc32.pl | 1 - test_regress/t/t_var_pins_sc64.pl | 1 - test_regress/t/t_var_pinsizes.v | 1 - test_sc/{.cvsignore => .gitignore} | 0 test_sc/Makefile | 3 +- test_sc/Makefile_obj | 2 +- test_sp/{.cvsignore => .gitignore} | 0 test_sp/Makefile | 3 +- test_sp/Makefile_obj | 2 +- test_sp/sc_main.cpp | 4 +- test_v/input.vc | 4 +- test_v/t.v | 3 +- test_v/t_arith.v | 3 +- test_v/t_case.v | 3 +- test_v/t_chg.v | 5 +- test_v/t_clk.v | 5 +- test_v/t_clk_flop.v | 3 +- test_v/t_clk_two.v | 1 - test_v/t_func.v | 3 +- test_v/t_func_grey2bin.v | 8 ++-- test_v/t_initial.v | 7 ++- test_v/t_initial_inc.v | 1 - test_v/t_inst.v | 5 +- test_v/t_inst_a.v | 3 +- test_v/t_inst_b.v | 3 +- test_v/t_loop.v | 3 +- test_v/t_mem.v | 7 ++- test_v/t_netlist.v | 3 +- test_v/t_param.v | 7 ++- test_v/t_param_a.v | 5 +- test_v/t_param_b.v | 3 +- test_v/t_rnd.v | 3 +- test_v/t_task.v | 3 +- test_v/top.v | 5 +- test_vcs/{.cvsignore => .gitignore} | 0 test_vcs/Makefile | 1 - test_vcs/bench.v | 1 - test_verilated/{.cvsignore => .gitignore} | 0 test_verilated/Makefile | 3 +- test_verilated/Makefile_obj | 2 +- test_verilated/sim_main.cpp | 1 - test_verilated/sim_main.v | 3 +- test_verilated/vgen.pl | 16 +++---- 658 files changed, 636 insertions(+), 1187 deletions(-) rename .cvsignore => .gitignore (94%) rename include/{.cvsignore => .gitignore} (100%) create mode 100644 nodist/leakchecking.txt rename src/{.cvsignore => .gitignore} (100%) rename test_c/{.cvsignore => .gitignore} (100%) rename test_regress/{.cvsignore => .gitignore} (100%) rename test_sc/{.cvsignore => .gitignore} (100%) rename test_sp/{.cvsignore => .gitignore} (100%) rename test_vcs/{.cvsignore => .gitignore} (100%) rename test_verilated/{.cvsignore => .gitignore} (100%) diff --git a/.cvsignore b/.gitignore similarity index 94% rename from .cvsignore rename to .gitignore index 154a707dd..709d8cbff 100644 --- a/.cvsignore +++ b/.gitignore @@ -7,7 +7,7 @@ *.1 *.tmp *.tex -Makefile +/Makefile README config.cache config.status diff --git a/Changes b/Changes index f47363b41..f5ddc54b2 100644 --- a/Changes +++ b/Changes @@ -1244,8 +1244,6 @@ of input ports exists for tracing. **** First code written. ---------------------------------------------------------------------- -$Id$ ----------------------------------------------------------------------- This uses outline mode in Emacs. See C-h m [M-x describe-mode]. diff --git a/Makefile.in b/Makefile.in index 435a50b53..50f7ac776 100644 --- a/Makefile.in +++ b/Makefile.in @@ -1,24 +1,23 @@ -# $Id$ #***************************************************************************** # DESCRIPTION: Verilator top level: Makefile pre-configure version -# -# This file is part of Verilator. -# +# +# This file is part of Verilator. +# # Author: Wilson Snyder -# +# # Code available from: http://www.veripool.org/verilator -# +# #***************************************************************************** -# +# # Copyright 2003-2008 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # General Public License or the Perl Artistic License. -# +# # Verilator is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# #****************************************************************************/ # # make all to compile and build Verilator. @@ -38,7 +37,7 @@ # source and built the program without creating any other files, # `make distclean' should leave only the files that were in the # distribution. -# +# # make maintainer-clean # Delete everything from the current directory that can be # reconstructed with this Makefile. This typically includes @@ -62,7 +61,7 @@ TEXI2DVI = texi2dvi PERL = @PERL@ # Destination prefix for RPMs -DESTDIR = +DESTDIR = #### Don't edit: You're much better using configure switches to set these prefix = @prefix@ @@ -101,7 +100,7 @@ DISTDEP = info Makefile # Files to distribute. DISTBIN = $(wildcard bin/verilator-*) -DISTFILES_INC = $(INFOS) .cvsignore COPYING *.in *.ac \ +DISTFILES_INC = $(INFOS) .gitignore COPYING *.in *.ac \ Changes README TODO \ MANIFEST.SKIP \ bin/* \ @@ -321,7 +320,7 @@ clean mostlyclean distclean maintainer-clean maintainer-copy:: done clean mostlyclean distclean maintainer-clean:: - rm -f $(SCRIPTS) *.tmp + rm -f $(SCRIPTS) *.tmp rm -f *.aux *.cp *.cps *.dvi *.fn *.fns *.ky *.kys *.log rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas diff --git a/TODO b/TODO index 39cf96e27..2114adc6f 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: List of To Do issues. // // Copyright 2004-2008 by Wilson Snyder. This program is free software; you can @@ -7,7 +6,7 @@ Features: - Finish 3.400 new ordering fixes + Finish 3.400 new ordering fixes Latch optimizations {Need here} Task I/Os connecting to non-simple variables. Fix nested casez statements expanding into to huge C++. [JeanPaul Vanitegem] @@ -50,7 +49,7 @@ Testing: Usability: Better reporting of unopt problems, including what lines of code - Report more errors (all of them?) before exiting [Eugene Weber] + Report more errors (all of them?) before exiting [Eugene Weber] Internal Code: Eliminate the AstNUser* passed to all visitors; its only needed in V3Width, @@ -69,7 +68,7 @@ Performance: Multithreaded execution Bit-multiply for faster bit swapping and a=b[1,3,2] random bit reorderings. Move _last sets and all other combo logic inside master - if() that triggers on all possible sense items + if() that triggers on all possible sense items Rewrite and combine V3Life, V3Subst If block temp only ever set in one place to constant, propagate it Used in t_mem for array delayed assignments @@ -139,15 +138,15 @@ Selectable SystemC types based on widths (see notes below) c) a conditional whose possible values are (a) or (b) 2) One can lose that fact that a node is a tristate node. This happens - if a tristate node is assigned to a 'standard' node, or is used on + if a tristate node is assigned to a 'standard' node, or is used on RHS of a conditional. The following infer tristate signals: - a) inout - b) tri + a) inout + b) tri c) assigning to 'Z' (maybe through a conditional) Note: tristate-ness of an output port determined only by statements in the module (not the instances it calls) - + 4) Tristate variables can't be multidimensional arrays - 5) Only check tristate contention between modules (not within!) + 5) Only check tristate contention between modules (not within!) 6) Only simple compares with 'Z' are allowed (===) diff --git a/bin/verilator b/bin/verilator index f486bf535..f0386032b 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1,7 +1,6 @@ : # -*-Mode: perl;-*- use perl, wherever it is eval 'exec perl -wS $0 ${1+"$@"}' if 0; -# $Id$ ###################################################################### # # Copyright 2003-2008 by Wilson Snyder. This program is free software; you can @@ -84,7 +83,6 @@ run ($vcmd); #---------------------------------------------------------------------- sub usage { - print '$Revision$$Date$ ', "\n"; pod2usage(-exitstatus=>2, -verbose=>2); } @@ -915,7 +913,7 @@ example: unsigned int main_time = 0; // Current simulation time double sc_time_stamp () { // Called by $time in Verilog - return main_time; + return main_time; } int main() { diff --git a/bin/verilator_difftree b/bin/verilator_difftree index 76115939d..6240dc52b 100755 --- a/bin/verilator_difftree +++ b/bin/verilator_difftree @@ -1,7 +1,6 @@ : # -*-Mode: perl;-*- use perl, wherever it is eval 'exec perl -wS $0 ${1+"$@"}' if 0; -# $Id$ ###################################################################### # # Copyright 2005-2008 by Wilson Snyder . This @@ -115,7 +114,6 @@ sub filter { #---------------------------------------------------------------------- sub usage { - print '$Id$ ', "\n"; pod2usage(-verbose=>2, -exitval => 2); exit (1); } @@ -130,7 +128,7 @@ sub parameter { $Opt_A = $param; } elsif (!defined $Opt_B) { $Opt_B = $param; - } else { + } else { die "%Error: Unknown parameter: $param\n"; } } diff --git a/bin/verilator_includer b/bin/verilator_includer index bb0cb2852..18132e77b 100755 --- a/bin/verilator_includer +++ b/bin/verilator_includer @@ -1,7 +1,6 @@ : # -*-Mode: perl;-*- use perl, wherever it is eval 'exec perl -wS $0 ${1+"$@"}' if 0; -# $Id$ # DESCRIPTION: Print include statements for each ARGV # # Copyright 2003-2008 by Wilson Snyder. This program is free software; you can diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index 488c98950..d4f058161 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -1,7 +1,6 @@ : # -*-Mode: perl;-*- use perl, wherever it is eval 'exec perl -wS $0 ${1+"$@"}' if 0; -# $Id$ ###################################################################### # # Copyright 2007-2008 by Wilson Snyder . This @@ -50,7 +49,6 @@ profcfunc($Opt_File); #---------------------------------------------------------------------- sub usage { - print '$Id$ ', "\n"; pod2usage(-verbose=>2, -exitval => 2); exit (1); } @@ -63,7 +61,7 @@ sub parameter { my $param = shift; if (!defined $Opt_File) { $Opt_File = $param; - } else { + } else { die "%Error: Unknown parameter: $param\n"; } } diff --git a/configure.ac b/configure.ac index 67a1a9dd3..5f93e78a4 100644 --- a/configure.ac +++ b/configure.ac @@ -1,10 +1,8 @@ -dnl $Id$ dnl DESCRIPTION: Process this file with autoconf to produce a configure script. dnl Copyright 2003-2008 by Wilson Snyder. This program is free software; you can dnl redistribute it and/or modify it under the terms of either the GNU dnl General Public License or the Perl Artistic License. -AC_REVISION($Revision$)dnl AC_INIT(src/Verilator.cpp) AC_CONFIG_HEADER(src/config_build.h) diff --git a/include/.cvsignore b/include/.gitignore similarity index 100% rename from include/.cvsignore rename to include/.gitignore diff --git a/include/verilated.cpp b/include/verilated.cpp index 89e6b3dcc..a94ee996d 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -1,4 +1,4 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- //************************************************************************* // // Copyright 2003-2008 by Wilson Snyder. This program is free software; you can @@ -9,7 +9,7 @@ // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. -// +// //========================================================================= /// /// \file @@ -86,7 +86,7 @@ IData VL_RAND_RESET_I(int outBits) { if (Verilated::randReset()!=1) { // if 2, randomize data = VL_RAND32(); } - if (outBits<32) data &= VL_MASK_I(outBits); + if (outBits<32) data &= VL_MASK_I(outBits); return data; } @@ -96,7 +96,7 @@ QData VL_RAND_RESET_Q(int outBits) { if (Verilated::randReset()!=1) { // if 2, randomize data = ((QData)VL_RAND32()< len) { if (strp) delete [] strp; strp = new char[newlen]; diff --git a/include/verilated.h b/include/verilated.h index 7b51cd9f0..935477b13 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -1,4 +1,4 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- //************************************************************************* // // Copyright 2003-2008 by Wilson Snyder. This program is free software; you can @@ -9,7 +9,7 @@ // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. -// +// //************************************************************************* /// /// \file @@ -129,7 +129,7 @@ struct Verilated { // Extern Vars // Below two are used as bool, but having as uint32_t avoids conversion time private: - static int s_randReset; ///< Random reset: 0=all 0s, 1=all 1s, 2=random + static int s_randReset; ///< Random reset: 0=all 0s, 1=all 1s, 2=random static int s_debug; ///< See accessors... only when VL_DEBUG set static bool s_calcUnusedSigs; ///< Waves file on, need all signals calculated static bool s_gotFinish; ///< A $finish statement executed @@ -152,7 +152,7 @@ public: #endif /// Internal: Create a new module name by concatenating two strings static const char* catName(const char* n1, const char* n2); // Returns new'ed data - /// Enable calculation of unused signals + /// Enable calculation of unused signals static void calcUnusedSigs(bool flag) { s_calcUnusedSigs=flag; } static bool calcUnusedSigs() { return s_calcUnusedSigs; } ///< Return calcUnusedSigs value /// Did the simulation $finish? @@ -165,7 +165,7 @@ public: /// Enable/disable assertions static void assertOn(bool flag) { s_assertOn=flag; } static bool assertOn() { return s_assertOn; } -}; +}; //========================================================================= // Extern functions -- User may override -- See verilated.cpp @@ -236,7 +236,7 @@ static inline QData VL_EXTENDSIGN_Q(int lbits, QData lhs) { return (-((lhs)&(VL // Debugging prints static inline void _VL_DEBUG_PRINT_W(int lbits, WDataInP iwp) { - printf(" Data: w%d: ", lbits); + printf(" Data: w%d: ", lbits); for (int i=VL_WORDS_I(lbits)-1; i>=0; i--) { printf("%08x ",iwp[i]); } printf("\n"); } @@ -878,7 +878,7 @@ static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) { return out; } -#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs) +#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs) static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) { if (lhs==0) return 0; @@ -896,23 +896,23 @@ static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) { // INTERNAL: Stuff LHS bit 0++ into OUTPUT at specified offset // ld may be "dirty", output is clean -static inline void _VL_INSERT_II(int, CData& lhsr, IData ld, int hbit, int lbit) { +static inline void _VL_INSERT_II(int, CData& lhsr, IData ld, int hbit, int lbit) { IData insmask = (VL_MASK_I(hbit-lbit+1))<lbits) { // Outside bounds, + if (msb>lbits) { // Outside bounds, for (int i=0; i // Linux and most flavors # include // Solaris typedef uint8_t vluint8_t; ///< 32-bit unsigned type typedef uint16_t vluint16_t; ///< 32-bit unsigned type -typedef int vlsint32_t; ///< 32-bit signed type +typedef int vlsint32_t; ///< 32-bit signed type typedef uint32_t vluint32_t; ///< 32-bit signed type -typedef long long vlsint64_t; ///< 64-bit signed type +typedef long long vlsint64_t; ///< 64-bit signed type typedef unsigned long long vluint64_t; ///< 64-bit unsigned type #endif diff --git a/install-sh b/install-sh index ebc66913e..f98503c2a 100644 --- a/install-sh +++ b/install-sh @@ -115,7 +115,7 @@ fi if [ x"$dir_arg" != x ]; then dst=$src src="" - + if [ -d $dst ]; then instcmd=: else diff --git a/mkinstalldirs b/mkinstalldirs index f82d8f1ee..f945dbf2b 100644 --- a/mkinstalldirs +++ b/mkinstalldirs @@ -4,8 +4,6 @@ # Created: 1993-05-16 # Public domain -# $Id:$ - errstatus=0 for file diff --git a/nodist/bisonreader b/nodist/bisonreader index 75eed82d0..be781d350 100755 --- a/nodist/bisonreader +++ b/nodist/bisonreader @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -#$Id$ ###################################################################### # # Copyright 2007-2008 by Wilson Snyder. @@ -7,16 +6,16 @@ # This program is free software; you can redistribute it and/or modify # it under the terms of either the GNU General Public License or the # Perl Artistic License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the Perl Artistic License # along with this module; see the file COPYING. If not, see # www.cpan.org -# +# ###################################################################### # DESCRIPTION: Debugging of bison output diff --git a/nodist/dot_importer b/nodist/dot_importer index 8b4b8b86c..76f5e09c8 100755 --- a/nodist/dot_importer +++ b/nodist/dot_importer @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -# $Id$ ###################################################################### # # Copyright 2005-2008 by Wilson Snyder . This @@ -50,7 +49,6 @@ cwrite ("graph_export.cpp"); #---------------------------------------------------------------------- sub usage { - print '$Id$ ', "\n"; pod2usage(-verbose=>2, -exitval => 2); exit (1); } @@ -120,7 +118,7 @@ sub cwrite { foreach my $edge (@Edges) { $fh->printf(" new V3GraphEdge(gp, %s, %s, %s, %s);\n", $edge->{from}, $edge->{to}, - $edge->{weight}, $edge->{cutable}?"true":"false"); + $edge->{weight}, $edge->{cutable}?"true":"false"); } $fh->print("}\n"); } diff --git a/nodist/dot_pruner b/nodist/dot_pruner index 0faa2b3bf..46806d056 100755 --- a/nodist/dot_pruner +++ b/nodist/dot_pruner @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -# $Id$ ###################################################################### # # Copyright 2005-2008 by Wilson Snyder . This @@ -55,7 +54,6 @@ dotwrite(); #---------------------------------------------------------------------- sub usage { - print '$Id$ ', "\n"; pod2usage(-verbose=>2, -exitval => 2); exit (1); } @@ -175,7 +173,7 @@ __END__ =head1 NAME -dot_pruner - +dot_pruner - =head1 SYNOPSIS diff --git a/nodist/invoke_ncverilog b/nodist/invoke_ncverilog index 15aa2d9ae..d4a5c2691 100755 --- a/nodist/invoke_ncverilog +++ b/nodist/invoke_ncverilog @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -# $Id$ ###################################################################### # # Copyright 2007-2008 by Wilson Snyder . This diff --git a/nodist/leakchecking.txt b/nodist/leakchecking.txt new file mode 100644 index 000000000..c688bab47 --- /dev/null +++ b/nodist/leakchecking.txt @@ -0,0 +1,4 @@ +export GLIBCPP_FORCE_NEW=1 +compile with -DVL_LEAK_CHECKS +valgrind --tool=memcheck --leak-check=yes /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg -MMD --bin /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg --cc -f /home/wsnyder/src/verilator/v4/verilator/test_c/../test_v/input.vc top.v --no-skip-identical 2>&1 | tee ~/d/aa +valgrind --tool=memcheck --leak-check=yes /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg -MMD --bin /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg --cc /home/wsnyder/src/verilator/v4/verilator/test_regress/t/t_case_huge.v --no-skip-identical -I/home/wsnyder/src/verilator/v4/verilator/test_regress/t 2>&1 | tee ~/d/aa diff --git a/nodist/vtree_importer b/nodist/vtree_importer index e59eeb554..beb39edf0 100755 --- a/nodist/vtree_importer +++ b/nodist/vtree_importer @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -# $Id$ ###################################################################### # # Copyright 2005-2008 by Wilson Snyder . This @@ -52,7 +51,6 @@ print '(query-replace-regexp "(\\([0-9a-z_]+\\))" "\\1" nil nil nil)',"\n"; #---------------------------------------------------------------------- sub usage { - print '$Id$ ', "\n"; pod2usage(-verbose=>2, -exitval => 2); exit (1); } @@ -292,7 +290,7 @@ sub p_var { } p "\t"; { - local $Avoid_Hex=1; + local $Avoid_Hex=1; t1; } p "\t"; @@ -322,7 +320,7 @@ __END__ =head1 NAME -vtree_importer - +vtree_importer - =head1 SYNOPSIS diff --git a/readme.texi b/readme.texi index 1ae6a0706..221aea034 100644 --- a/readme.texi +++ b/readme.texi @@ -1,6 +1,5 @@ \input texinfo @c -*-texinfo-*- @c %**start of header -$c $Id$ @setfilename readme.info @settitle Verilator Installation @c %**end of header @@ -15,13 +14,13 @@ $c $Id$ This is the Verilator Package. @menu -* Copyright:: -* Description:: -* Obtaining Distribution:: -* Directory Structure:: -* Supported Systems:: -* Installation:: -* Limitations:: +* Copyright:: +* Description:: +* Obtaining Distribution:: +* Directory Structure:: +* Supported Systems:: +* Installation:: +* Limitations:: @end menu @node Copyright, Description, Top, Top @@ -56,7 +55,7 @@ The resulting executable will perform the actual simulation. @node Obtaining Distribution, Directory Structure, Description, Top @section Obtaining Distribution -The latest version is available at +The latest version is available at @uref{http://www.veripool.org/verilator} Download the latest package from that site, and decompress. diff --git a/src/.cvsignore b/src/.gitignore similarity index 100% rename from src/.cvsignore rename to src/.gitignore diff --git a/src/Makefile.in b/src/Makefile.in index 364676b09..dda9403e3 100644 --- a/src/Makefile.in +++ b/src/Makefile.in @@ -1,4 +1,4 @@ -# $Id$ */ +# -*- Makefile -*- #***************************************************************************** # # DESCRIPTION: Verilator: Makefile for verilog source @@ -40,7 +40,7 @@ export OBJCACHE_HOSTS := $(shell rschedule --no-allow-reserved --similar hostnam endif ifeq ($(OBJCACHE_HOSTS),) -export OBJCACHE := +export OBJCACHE := else export OBJCACHE_JOBS := -j $(shell objcache --jobs "$(OBJCACHE_HOSTS)") export OBJCACHE := @objcache --read --write @@ -74,7 +74,7 @@ prefiles:: ifeq ($(VERILATOR_AUTHOR_SITE),1) # Local... Else don't burden users prefiles:: config_rev.h # This output goes into srcdir, as we need to distribute it as part of the kit. -config_rev.h: config_rev.pl .svn/entries +config_rev.h: config_rev.pl ../.git/index $(PERL) config_rev.pl . >$@ endif diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index 9a54ef930..9b2338a48 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -1,4 +1,4 @@ -# $Id$ -*- Makefile -*- +# -*- Makefile -*- #***************************************************************************** # # DESCRIPTION: Verilator: Makefile for verilog source diff --git a/src/V3Active.cpp b/src/V3Active.cpp index fa5904385..8b62e2cfa 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Break always into sensitivity active domains // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Active's Transformations: -// +// // Note this can be called multiple times. // Create a IACTIVE(initial), SACTIVE(combo) // ALWAYS: Remove any-edges from sense list diff --git a/src/V3Active.h b/src/V3Active.h index 58ee1ef50..2c8a185df 100644 --- a/src/V3Active.h +++ b/src/V3Active.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Break always into sensitivity block domains // diff --git a/src/V3ActiveTop.cpp b/src/V3ActiveTop.cpp index 7e0388f23..fe534e24f 100644 --- a/src/V3ActiveTop.cpp +++ b/src/V3ActiveTop.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Break always into sensitivity active domains // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Active's Transformations: -// +// // Note this can be called multiple times. // Across all ACTIVES // SenTrees are now under each ACTIVE statement, we want them global: diff --git a/src/V3ActiveTop.h b/src/V3ActiveTop.h index e1f40758c..509eb9bb1 100644 --- a/src/V3ActiveTop.h +++ b/src/V3ActiveTop.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Break always into sensitivity block domains // diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index 502b3cf76..993c33adb 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Collect and print statistics // @@ -106,7 +105,7 @@ private: sentreep->unlinkFrBack(); // AstNode* bodysp = NULL; - bool selfDestruct = false; + bool selfDestruct = false; if (AstPslCover* snodep = nodep->castPslCover()) { if (!v3Global.opt.coverageUser()) { selfDestruct = true; diff --git a/src/V3Assert.h b/src/V3Assert.h index f2c230b5c..e183dedd4 100644 --- a/src/V3Assert.h +++ b/src/V3Assert.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Assertion expansion // diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp index 8375faef2..f1e37b0f7 100644 --- a/src/V3AssertPre.cpp +++ b/src/V3AssertPre.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Collect and print statistics // diff --git a/src/V3AssertPre.h b/src/V3AssertPre.h index 40725ed16..c14df42ae 100644 --- a/src/V3AssertPre.h +++ b/src/V3AssertPre.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Assertion pre-expansion // diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index 01443ea9f..d2bd46310 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Ast node structures // @@ -255,8 +254,8 @@ void AstNode::addNextHere(AstNode* newp) { void AstNode::setOp1p(AstNode* newp) { UASSERT(newp,"Null item passed to setOp1p\n"); UDEBUGONLY(if (m_op1p) this->v3fatalSrc("Adding to non-empty, non-list op1");); - UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); - UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op1");); + UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); + UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op1");); this->debugTreeChange("-setOp1pThs: ", __LINE__, false); newp->debugTreeChange("-setOp1pNew: ", __LINE__, true); m_op1p = newp; @@ -268,8 +267,8 @@ void AstNode::setOp1p(AstNode* newp) { void AstNode::setOp2p(AstNode* newp) { UASSERT(newp,"Null item passed to setOp2p\n"); UDEBUGONLY(if (m_op2p) this->v3fatalSrc("Adding to non-empty, non-list op2");); - UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); - UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op2");); + UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); + UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op2");); this->debugTreeChange("-setOp2pThs: ", __LINE__, false); newp->debugTreeChange("-setOp2pNew: ", __LINE__, true); m_op2p = newp; @@ -281,8 +280,8 @@ void AstNode::setOp2p(AstNode* newp) { void AstNode::setOp3p(AstNode* newp) { UASSERT(newp,"Null item passed to setOp3p\n"); UDEBUGONLY(if (m_op3p) this->v3fatalSrc("Adding to non-empty, non-list op3");); - UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); - UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op3");); + UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); + UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op3");); this->debugTreeChange("-setOp3pThs: ", __LINE__, false); newp->debugTreeChange("-setOp3pNew: ", __LINE__, true); m_op3p = newp; @@ -294,8 +293,8 @@ void AstNode::setOp3p(AstNode* newp) { void AstNode::setOp4p(AstNode* newp) { UASSERT(newp,"Null item passed to setOp4p\n"); UDEBUGONLY(if (m_op4p) this->v3fatalSrc("Adding to non-empty, non-list op4");); - UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); - UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op4");); + UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); + UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op4");); this->debugTreeChange("-setOp4pThs: ", __LINE__, false); newp->debugTreeChange("-setOp4pNew: ", __LINE__, true); m_op4p = newp; diff --git a/src/V3Ast.h b/src/V3Ast.h index fa5f23632..20c6c7458 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Ast node structure // @@ -1009,7 +1009,7 @@ public: AstNodeFTaskRef(FileLine* fl, AstNode* namep, AstNode* pinsp) :AstNode(fl) , m_taskp(NULL) { - setOp1p(namep); addNOp2p(pinsp); + setOp1p(namep); addNOp2p(pinsp); } virtual ~AstNodeFTaskRef() {} virtual bool broken() const { return m_taskp && !m_taskp->brokeExists(); } diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 965f4db4b..94385e511 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Ast node structures // diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index b9bb67c57..18b9a2474 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Ast node structure // @@ -254,7 +254,7 @@ private: m_sc=false; m_scClocked=false; m_scSensitive=false; m_usedClock=false; m_usedParam=false; m_sigPublic=false; m_sigModPublic=false; - m_funcLocal=false; m_funcReturn=false; + m_funcLocal=false; m_funcReturn=false; m_attrClockEn=false; m_attrIsolateAssign=false; m_fileDescr=false; m_isConst=false; m_isStatic=false; m_trace=false; @@ -554,7 +554,7 @@ public: virtual AstNode* clone() { return new AstVarXRef(*this);} virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); } virtual void dump(ostream& str); - string dotted() const { return m_dotted; } + string dotted() const { return m_dotted; } string prettyDotted() const { return prettyName(dotted()); } string inlinedDots() const { return m_inlinedDots; } void inlinedDots(const string& flag) { m_inlinedDots = flag; } @@ -755,7 +755,7 @@ public: AstNode* stmtsp() const { return op1p()->castNode(); } // op1 = List of statements void addStmtp(AstNode* nodep) { addOp1p(nodep); } }; - + struct AstGenerate : public AstNode { // A Generate/end block // Parents: MODULE @@ -1117,7 +1117,7 @@ private: public: AstCoverDecl(FileLine* fl, int column, const string& type, const string& comment) : AstNodeStmt(fl) { - m_text = comment; m_typeText = type; m_column = column; + m_text = comment; m_typeText = type; m_column = column; } virtual ~AstCoverDecl() {} virtual AstType type() const { return AstType::COVERDECL;} diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp index ef6ed81e7..61d409aca 100644 --- a/src/V3Begin.cpp +++ b/src/V3Begin.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Removal of named begin blocks // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Begin's Transformations: -// +// // Each module: // Look for BEGINs // BEGIN(VAR...) -> VAR ... {renamed} diff --git a/src/V3Begin.h b/src/V3Begin.h index 196174c1f..6951ed8b7 100644 --- a/src/V3Begin.h +++ b/src/V3Begin.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Removal of named begin blocks // diff --git a/src/V3Branch.cpp b/src/V3Branch.cpp index 455608014..ebc780e02 100644 --- a/src/V3Branch.cpp +++ b/src/V3Branch.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Branch prediction // diff --git a/src/V3Branch.h b/src/V3Branch.h index 7b4fac8fe..0e016c14d 100644 --- a/src/V3Branch.h +++ b/src/V3Branch.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Branch prediction // diff --git a/src/V3Broken.cpp b/src/V3Broken.cpp index 3cadd4f46..c07aa5d53 100644 --- a/src/V3Broken.cpp +++ b/src/V3Broken.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Find broken links in tree // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Broken's Transformations: -// +// // Entire netlist // Mark all nodes // Check all links point to marked nodes diff --git a/src/V3Broken.h b/src/V3Broken.h index e17d2e39c..66170d182 100644 --- a/src/V3Broken.h +++ b/src/V3Broken.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Find broken links in tree // diff --git a/src/V3Case.cpp b/src/V3Case.cpp index fae1088d8..5b8c8436c 100644 --- a/src/V3Case.cpp +++ b/src/V3Case.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Break case statements up and add Unknown assigns // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Case's Transformations: -// +// // Each module: // TBD: Eliminate tristates by adding __in, __inen, __en wires in parallel // Need __en in changed list if a signal is on the LHS of a assign @@ -235,7 +234,7 @@ private: // new AstConst(cexprp->fileline(), nummask)); AstNode* and1p = new AstSel(cexprp->fileline(), cexprp->cloneTree(false), msb, 1); - AstNode* eqp = new AstNeq(cexprp->fileline(), + AstNode* eqp = new AstNeq(cexprp->fileline(), new AstConst(cexprp->fileline(), 0), and1p); AstIf* ifp = new AstIf(cexprp->fileline(), eqp, tree1p, tree0p); @@ -293,7 +292,7 @@ private: for (AstNode* icondp = itemp->condsp(); icondp!=NULL; icondp=icondNextp) { icondNextp = icondp->nextp(); icondp->unlinkFrBack(); - + AstNode* and1p; AstNode* and2p; AstConst* iconstp = icondp->castConst(); @@ -305,7 +304,7 @@ private: numval.opBitsOne(iconstp->num()); and1p = new AstAnd(itemp->fileline(), cexprp->cloneTree(false), new AstConst(itemp->fileline(), nummask)); - and2p = new AstAnd(itemp->fileline(), + and2p = new AstAnd(itemp->fileline(), new AstConst(itemp->fileline(), numval), new AstConst(itemp->fileline(), nummask)); icondp->deleteTree(); icondp=NULL; iconstp=NULL; diff --git a/src/V3Case.h b/src/V3Case.h index fc94a2dd2..daf852e7f 100644 --- a/src/V3Case.h +++ b/src/V3Case.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Break case statements up and add Unknown assigns // diff --git a/src/V3Cast.cpp b/src/V3Cast.cpp index c786c0939..22c1ab2ef 100644 --- a/src/V3Cast.cpp +++ b/src/V3Cast.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add C++ casts across expression size changes // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Cast's Transformations: -// +// // Each module: // For each math operator, if above operator requires 32 bits, // and this isn't, cast to 32 bits. @@ -148,7 +147,7 @@ private: && nodep->backp()->width() && castSize(nodep) != castSize(nodep->varp())) { // Cast vars to IData first, else below has upper bits wrongly set - // CData x=3; out = (QData)(x<<30); + // CData x=3; out = (QData)(x<<30); insertCast (nodep, castSize(nodep)); } nodep->user(1); diff --git a/src/V3Cast.h b/src/V3Cast.h index 47635bec1..b1683857c 100644 --- a/src/V3Cast.h +++ b/src/V3Cast.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Add C++ casts across expression size changes // diff --git a/src/V3Changed.cpp b/src/V3Changed.cpp index 75051b2bc..b06bf2b45 100644 --- a/src/V3Changed.cpp +++ b/src/V3Changed.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add temporaries, such as for changed nodes // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Changed's Transformations: -// +// // Each module: // Each combo block // For each variable that comes from combo block and is generated AFTER a usage diff --git a/src/V3Changed.h b/src/V3Changed.h index adcf61d57..fdd05ff4f 100644 --- a/src/V3Changed.h +++ b/src/V3Changed.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Pre C-Emit stage changes // diff --git a/src/V3Clean.cpp b/src/V3Clean.cpp index 9c429e9f9..4c9600ea3 100644 --- a/src/V3Clean.cpp +++ b/src/V3Clean.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add temporaries, such as for clean nodes // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Clean's Transformations: -// +// // Each module: // For each math operator, if it requires a clean operand, // and the operand is dirty, insert a CLEAN node. @@ -55,7 +54,7 @@ private: // ENUMS enum CleanState { UNKNOWN, CLEAN, DIRTY }; - + // METHODS // Width resetting int cppWidth(AstNode* nodep) { diff --git a/src/V3Clean.h b/src/V3Clean.h index f84d6d5e1..de5269b61 100644 --- a/src/V3Clean.h +++ b/src/V3Clean.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Pre C-Emit stage changes // diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp index b46a5e8f0..00fd2cf7f 100644 --- a/src/V3Clock.cpp +++ b/src/V3Clock.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Clock's Transformations: -// +// // Top Scope: // Check created ACTIVEs // Compress adjacent ACTIVEs with same sensitivity list @@ -416,7 +415,7 @@ private: new AstConst(fl, 1))); preUntilp->addNext(new AstAssign(fl, new AstVarRef(fl, countVarp, true), new AstConst(fl, 0))); - + // Add stable variables & preinits AstNode* setChglastp = NULL; for (AstVarRef* varrefp = nodep->stablesp(); varrefp; varrefp=varrefp->nextp()->castVarRef()) { diff --git a/src/V3Clock.h b/src/V3Clock.h index 315dbb2f2..de54e0af7 100644 --- a/src/V3Clock.h +++ b/src/V3Clock.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion // diff --git a/src/V3Combine.cpp b/src/V3Combine.cpp index 279cdca04..164c90d81 100644 --- a/src/V3Combine.cpp +++ b/src/V3Combine.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Combine common code into functions // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Combine's Transformations: -// +// // For every function that we spit out // Examine code to find largest common blocks // Hash each node depth first @@ -32,7 +31,7 @@ // Make new function // Move common block to function // Replace each common block ref with funccall -// +// //************************************************************************* #include "config_build.h" diff --git a/src/V3Combine.h b/src/V3Combine.h index 61cbdd2a9..408944158 100644 --- a/src/V3Combine.h +++ b/src/V3Combine.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Combine common code into functions // diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 3b505d46f..d14155604 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Constant folding // @@ -102,7 +101,7 @@ private: bool m_wremove; // Inside scope, no assignw removal bool m_warn; // Output warnings bool m_cpp; // C++ conversions only - AstModule* m_modp; // Current module + AstModule* m_modp; // Current module AstNode* m_scopep; // Current scope //int debug() { return 9; } @@ -143,7 +142,7 @@ private: } bool operandIsTwo(AstNode* nodep) { return (nodep->castConst() - && nodep->width() <= VL_QUADSIZE + && nodep->width() <= VL_QUADSIZE && nodep->castConst()->asQuad()==2); } bool operandIsTwostate(AstNode* nodep) { @@ -745,7 +744,7 @@ private: // Recurse rather then calling node->iterate to prevent 2^n recursion! if (operandConcatMove(abConcp)) moveConcat(abConcp); bcConcp->deleteTree(); bcConcp=NULL; - } else { + } else { AstConcat* abConcp = nodep->lhsp()->castConcat(); abConcp->unlinkFrBack(); AstNode* ap = abConcp->lhsp()->unlinkFrBack(); AstNode* bp = abConcp->rhsp()->unlinkFrBack(); @@ -1017,7 +1016,7 @@ private: && nodep->ifsp() && nodep->elsesp()) { UINFO(4,"IF(NOT {x}) => IF(x) swapped if/else"<condp()->castNot()->lhsp()->unlinkFrBackWithNext(); - AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext(); + AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext(); AstNode* elsesp = nodep->elsesp()->unlinkFrBackWithNext(); AstIf* ifp = new AstIf(nodep->fileline(), condp, elsesp, ifsp); ifp->branchPred(nodep->branchPred().invert()); @@ -1038,7 +1037,7 @@ private: nodep->deleteTree(); nodep=NULL; } else if (0 // Disabled, as vpm assertions are faster without due to short-circuiting - && operandIfIf(nodep)) { + && operandIfIf(nodep)) { UINFO(0,"IF({a}) IF({b}) => IF({a} && {b})"<ifsp()->castNodeIf(); AstNode* condp = nodep->condp()->unlinkFrBack(); diff --git a/src/V3Const.h b/src/V3Const.h index 918e780ce..61b86614e 100644 --- a/src/V3Const.h +++ b/src/V3Const.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Propagate constants across AST // diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp index 004ab563a..0c6d2a4f1 100644 --- a/src/V3Coverage.cpp +++ b/src/V3Coverage.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Netlist (top level) functions // @@ -53,7 +52,7 @@ private: bool m_checkBlock; // Should this block get covered? AstModule* m_modp; // Current module to add statement to FileMap m_fileps; // Column counts for each fileline - + //int debug() { return 9; } // METHODS @@ -66,7 +65,7 @@ private: column = (it->second)++; } - AstCoverDecl* declp = new AstCoverDecl(fl, column, type, comment); + AstCoverDecl* declp = new AstCoverDecl(fl, column, type, comment); m_modp->addStmtp(declp); return new AstCoverInc(fl, declp); diff --git a/src/V3Coverage.h b/src/V3Coverage.h index 18b27082f..bc697ac8b 100644 --- a/src/V3Coverage.h +++ b/src/V3Coverage.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Coverage modules/signals together // diff --git a/src/V3Dead.cpp b/src/V3Dead.cpp index d6b3843f6..acdfcbdac 100644 --- a/src/V3Dead.cpp +++ b/src/V3Dead.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Dead code elimination // @@ -21,7 +20,7 @@ // DEAD TRANSFORMATIONS: // Remove any unreferenced modules // Remove any unreferenced variables -// +// //************************************************************************* #include "config_build.h" diff --git a/src/V3Dead.h b/src/V3Dead.h index 7f17a28dc..7ce5b8f82 100644 --- a/src/V3Dead.h +++ b/src/V3Dead.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Dead branch elimination // diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index 15234ed50..3202bd486 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add temporaries, such as for delayed nodes // @@ -19,9 +18,9 @@ // //************************************************************************* // V3Delayed's Transformations: -// +// // Each module: -// Replace ASSIGNDLY var, exp +// Replace ASSIGNDLY var, exp // With ASSIGNDLY newvar, exp // At top of block: VAR newvar // At bottom of block: ASSIGNW var newvar @@ -269,7 +268,7 @@ private: AstAlwaysPost* finalp = varrefp->varScopep()->user4p()->castNode()->castAlwaysPost(); if (!finalp) { finalp = new AstAlwaysPost(nodep->fileline(), NULL/*sens*/, NULL/*body*/); - UINFO(9," Created "<addStmtsp(finalp); varrefp->varScopep()->user4p(finalp); } @@ -284,7 +283,7 @@ private: new AstVarRef(nodep->fileline(), setvscp, false), NULL, NULL); - UINFO(9," Created "<addBodysp(postLogicp); finalp->user5p(setvscp); // Remember IF's vset variable finalp->user4p(postLogicp); // and the associated IF, as we may be able to reuse it @@ -347,7 +346,7 @@ private: virtual void visit(AstVarRef* nodep, AstNUser*) { if (!nodep->user2()) { // Not done yet nodep->user2(true); - + if (m_inDly && nodep->lvalue()) { UINFO(4,"AssignDlyVar: "<varp(), VU_DLY); @@ -401,7 +400,7 @@ private: m_activep->sensesp()); newactp->addStmtsp(prep); // Add to FRONT of statements newactp->addStmtsp(postp); - m_activep->addNext(newactp); + m_activep->addNext(newactp); dlyvscp->user2p(newactp); } AstVarRef* newrefp = new AstVarRef(nodep->fileline(), dlyvscp, true); diff --git a/src/V3Delayed.h b/src/V3Delayed.h index 058f97921..61e528458 100644 --- a/src/V3Delayed.h +++ b/src/V3Delayed.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Pre C-Emit stage changes // diff --git a/src/V3Depth.cpp b/src/V3Depth.cpp index f131113a5..0e4348e20 100644 --- a/src/V3Depth.cpp +++ b/src/V3Depth.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Prevent very deep expressions // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Depth's Transformations: -// +// // Each module: // For each wide OP, assign a temporary variable. // For each deep expression, assign expression to temporary. @@ -111,7 +110,7 @@ private: // We have some operator defines that use 2 parens, so += 2. m_depth += 2; if (m_depth>m_maxdepth) m_maxdepth=m_depth; - nodep->iterateChildren(*this); + nodep->iterateChildren(*this); m_depth -= 2; if (m_stmtp diff --git a/src/V3Depth.h b/src/V3Depth.h index 1d9a3bd2f..4b5eb0d74 100644 --- a/src/V3Depth.h +++ b/src/V3Depth.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Prevent very deep expressions // diff --git a/src/V3DepthBlock.cpp b/src/V3DepthBlock.cpp index d8f09a960..d052d1cb9 100644 --- a/src/V3DepthBlock.cpp +++ b/src/V3DepthBlock.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Prevent very deep expressions // @@ -19,7 +18,7 @@ // //************************************************************************* // V3DepthBlock's Transformations: -// +// // Each module: // For each deep block, create cfunc including that block. // diff --git a/src/V3DepthBlock.h b/src/V3DepthBlock.h index d1089966b..81c6b4ac5 100644 --- a/src/V3DepthBlock.h +++ b/src/V3DepthBlock.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Prevent very deep expressions // diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp index 1075bb498..f3c84c83a 100644 --- a/src/V3Descope.cpp +++ b/src/V3Descope.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Rename scope references to module-local references // @@ -24,7 +23,7 @@ // Change varref name() to be relative to current module // Remove varScopep() // This allows for better V3Combine'ing. -// +// //************************************************************************* #include "config_build.h" diff --git a/src/V3Descope.h b/src/V3Descope.h index 076e42149..4cb404e89 100644 --- a/src/V3Descope.h +++ b/src/V3Descope.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Rename scope references to module-local references // diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index 13daf8353..4b0f525c2 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Emit C++ for tree // @@ -80,9 +79,9 @@ public: // METHODS void displayEmit(AstDisplay* nodep); - string displayFormat(AstNode* widthNode, string in, + string displayFormat(AstNode* widthNode, string in, char fmtLetter, bool padZero, bool reallyString); - void displayArg(AstDisplay* dispp, AstNode** elistp, string fmt, char fmtLetter); + void displayArg(AstDisplay* dispp, AstNode** elistp, string fmt, char fmtLetter); void emitVarDecl(AstVar* nodep, const string& prefixIfImp); typedef enum {EVL_IO, EVL_SIG, EVL_TEMP, EVL_STATIC, EVL_ALL} EisWhich; @@ -212,7 +211,7 @@ public: } virtual void visit(AstCoverDecl* nodep, AstNUser*) { puts("__vlCoverInsert("); // As Declared in emitCoverageDecl - puts("&__Vcoverage["); + puts("&__Vcoverage["); puts(cvtToStr(m_coverIds.remap(nodep))); puts("]"); puts(", \""); puts(nodep->fileline()->filebasename()); puts("\""); puts(", "); puts(cvtToStr(nodep->fileline()->lineno())); @@ -639,7 +638,7 @@ class EmitCImp : EmitCStmts { puts(modClassName(m_modp)+"::"+nodep->name() +"("+cFuncArgs(nodep)+") {\n"); - puts("VL_DEBUG_IF(cout<<\" "); + puts("VL_DEBUG_IF(cout<<\" "); for (int i=0;ilevel();i++) { puts(" "); } puts(modClassName(m_modp)+"::"+nodep->name() +"\"<stmtsp(); nodep; nodep = nodep->nextp()) { if (AstCFunc* funcp = nodep->castCFunc()) { if (v3Global.opt.outputSplit() > 1 && splitSize() @@ -1739,7 +1738,7 @@ class EmitCTrace : EmitCStmts { puts("if (!Verilated::calcUnusedSigs()) vl_fatal(__FILE__,__LINE__,__FILE__,\"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.\");\n"); puts("t->traceInitThis (vlSymsp, vcdp, code);\n"); puts("}\n"); - + puts("void "+topClassName()+"::traceFull(SpTraceVcd* vcdp, void* userthis, uint32_t code) {\n"); puts("// Callback from vcd->dump()\n"); puts(topClassName()+"* t=("+topClassName()+"*)userthis;\n"); @@ -1909,7 +1908,7 @@ class EmitCTrace : EmitCStmts { } virtual void visit(AstCoverInc* nodep, AstNUser*) { } - + public: EmitCTrace(bool slow) { m_funcp = NULL; diff --git a/src/V3EmitC.h b/src/V3EmitC.h index 8377694ba..f31834b4a 100644 --- a/src/V3EmitC.h +++ b/src/V3EmitC.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Emit C++ code for module tree // diff --git a/src/V3EmitCBase.h b/src/V3EmitCBase.h index 27f4e5571..425424555 100644 --- a/src/V3EmitCBase.h +++ b/src/V3EmitCBase.h @@ -1,4 +1,4 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Emit C++ for tree // diff --git a/src/V3EmitCInlines.cpp b/src/V3EmitCInlines.cpp index ccd3dd7d0..b7b8610c3 100644 --- a/src/V3EmitCInlines.cpp +++ b/src/V3EmitCInlines.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Emit C++ for tree // diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index a843dfb27..d6a291a7c 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Emit C++ for tree // @@ -68,7 +67,7 @@ class EmitCSyms : EmitCBaseVisitor { virtual void visit(AstNetlist* nodep, AstNUser*) { // Collect list of scopes nodep->iterateChildren(*this); - + // Sort m_scopes by scope name sort(m_scopes.begin(), m_scopes.end(), CmpName()); // Output diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index f1bd01f88..dd03c3650 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Emit Makefile // diff --git a/src/V3EmitMk.h b/src/V3EmitMk.h index 497f7d3f0..49c10aa32 100644 --- a/src/V3EmitMk.h +++ b/src/V3EmitMk.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Emit Makefile // diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index 8af43a83e..e7b360347 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Emit Verilog from tree // diff --git a/src/V3EmitV.h b/src/V3EmitV.h index 7378cf61d..5e9647d46 100644 --- a/src/V3EmitV.h +++ b/src/V3EmitV.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +//-*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Emit Verilog code for module tree // diff --git a/src/V3Error.cpp b/src/V3Error.cpp index 860e84926..d24f0f2f8 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Error handling // @@ -47,7 +46,7 @@ bool V3Error::s_pretendError[V3ErrorCode::MAX]; struct v3errorIniter { v3errorIniter() { V3Error::init(); }; }; -v3errorIniter v3errorInit; +v3errorIniter v3errorInit; //###################################################################### // ErrorCode class functions @@ -203,7 +202,7 @@ void FileLine::deleteAllRemaining() { while (1) { FileLineCheckSet::iterator it=fileLineLeakChecks.begin(); if (it==fileLineLeakChecks.end()) break; - delete *it; + delete *it; // Operator delete will remove the iterated object from the list. // Eventually the list will be empty and terminate the loop. } diff --git a/src/V3Error.h b/src/V3Error.h index da7b495b5..a2b87b203 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Error handling // diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp index 16ddbdd45..de553994c 100644 --- a/src/V3Expand.cpp +++ b/src/V3Expand.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add temporaries, such as for expand nodes // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Expand's Transformations: -// +// // Each module: // Expand verilated.h macros into internal micro optimizations (RTL) // this will enable later optimizations. @@ -168,7 +167,7 @@ private: } return newp; } - + AstNode* newSelBitWord(AstNode* lsbp, int wordAdder) { // Return equation to get the VL_BITWORD of a constant or non-constant if (lsbp->castConst()) { @@ -355,7 +354,7 @@ private: AstNode* lowwordp = new AstWordSel (nodep->fromp()->fileline(), nodep->fromp()->cloneTree(true), newSelBitWord(nodep->lsbp(), 0)); - if (nodep->isQuad() && !lowwordp->isQuad()) lowwordp = new AstCast(nodep->fileline(), lowwordp, nodep); + if (nodep->isQuad() && !lowwordp->isQuad()) lowwordp = new AstCast(nodep->fileline(), lowwordp, nodep); AstNode* lowp = new AstShiftR (nodep->fileline(), lowwordp, newSelBitBit(nodep->lsbp()), @@ -368,7 +367,7 @@ private: new AstWordSel (nodep->fromp()->fileline(), nodep->fromp()->cloneTree(true), newSelBitWord(nodep->lsbp(), 1)); - if (nodep->isQuad() && !midwordp->isQuad()) midwordp = new AstCast(nodep->fileline(), midwordp, nodep); + if (nodep->isQuad() && !midwordp->isQuad()) midwordp = new AstCast(nodep->fileline(), midwordp, nodep); // If we're selecting bit zero, then all 32 bits in word 1 get shifted << by 32 bits // else we need to form the lower word, so we << by 31 or less // nbitsfromlow <= (lsb==0) ? 64-bitbit(lsb) : 32-bitbit(lsb) @@ -406,7 +405,7 @@ private: new AstWordSel (nodep->fromp()->fileline(), nodep->fromp()->cloneTree(true), newSelBitWord(nodep->lsbp(), 2)); - if (nodep->isQuad() && !hiwordp->isQuad()) hiwordp = new AstCast(nodep->fileline(), hiwordp, nodep); + if (nodep->isQuad() && !hiwordp->isQuad()) hiwordp = new AstCast(nodep->fileline(), hiwordp, nodep); AstNode* himayp = new AstShiftL (nodep->fileline(), hiwordp, @@ -434,7 +433,7 @@ private: UINFO(8," SEL->SHIFT "<fromp()->unlinkFrBack(); AstNode* lsbp = nodep->lsbp()->unlinkFrBack(); - if (nodep->isQuad() && !fromp->isQuad()) fromp = new AstCast(nodep->fileline(), fromp, nodep); + if (nodep->isQuad() && !fromp->isQuad()) fromp = new AstCast(nodep->fileline(), fromp, nodep); AstNode* newp = new AstShiftR (nodep->fileline(), fromp, dropCondBound(lsbp), @@ -504,7 +503,7 @@ private: bool destwide = lhsp->fromp()->isWide(); bool ones = nodep->rhsp()->isAllOnesV(); if (lhsp->lsbp()->castConst()) { - // The code should work without this constant test, but it won't + // The code should work without this constant test, but it won't // constify as nicely as we'd like. AstNode* rhsp = nodep->rhsp()->unlinkFrBack(); AstNode* destp = lhsp->fromp()->unlinkFrBack(); @@ -592,7 +591,7 @@ private: // For wide destp, we can either form a equation for every destination word, // with the appropriate long equation of if it's being written or not. // Or, we can use a LHS variable arraysel with non-constant index to set the vector. - // Doing the variable arraysel is better for globals and large arrays, + // Doing the variable arraysel is better for globals and large arrays, // doing every word is better for temporaries and if we're setting most words // since it may result in better substitution optimizations later. // This results in so much code, we're better off leaving a function call. @@ -630,7 +629,7 @@ private: //newp->dumpTree(cout,"- new: "); insertBefore(nodep,newp); return true; - } + } } } @@ -641,10 +640,10 @@ private: } else { UINFO(8," CONCAT "<lhsp()->unlinkFrBack(); - AstNode* rhsp = nodep->rhsp()->unlinkFrBack(); + AstNode* rhsp = nodep->rhsp()->unlinkFrBack(); int rhsshift = rhsp->widthMin(); - if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep); - if (nodep->isQuad() && !rhsp->isQuad()) rhsp = new AstCast(nodep->fileline(), rhsp, nodep); + if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep); + if (nodep->isQuad() && !rhsp->isQuad()) rhsp = new AstCast(nodep->fileline(), rhsp, nodep); AstNode* newp = new AstOr (nodep->fileline(), new AstShiftL (nodep->fileline(), lhsp, @@ -657,7 +656,7 @@ private: } bool expandWide (AstNodeAssign* nodep, AstConcat* rhsp) { UINFO(8," Wordize ASSIGN(CONCAT) "<rhsp()->widthMin(); // Sometimes doing the words backwards is preferrable. @@ -690,7 +689,7 @@ private: AstConst* constp = nodep->rhsp()->castConst(); if (!constp) nodep->v3fatalSrc("Replication value isn't a constant. Checked earlier!"); uint32_t times = constp->asInt(); - if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep); + if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep); newp = lhsp->cloneTree(true); for (unsigned repnum=1; repnumrhsp()->castVarRef() - // Until NEW_ORDERING, avoid making non-clocked logic into clocked, + // Until NEW_ORDERING, avoid making non-clocked logic into clocked, // as it slows down the verilator_sim_benchmark || (nodep->rhsp()->castNot() && nodep->rhsp()->castNot()->lhsp()->castVarRef() @@ -343,7 +342,7 @@ private: UINFO(5," VARREF to "<lvalue()) { + if (nodep->lvalue()) { new V3GraphEdge(&m_graph, m_logicVertexp, varvertexp, 1); } else { new V3GraphEdge(&m_graph, varvertexp, m_logicVertexp, 1); diff --git a/src/V3Gate.h b/src/V3Gate.h index a0089b39e..e4d051333 100644 --- a/src/V3Gate.h +++ b/src/V3Gate.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Break always into sensitivity block domains // diff --git a/src/V3GenClk.cpp b/src/V3GenClk.cpp index fea8ca1c0..4fa77374e 100644 --- a/src/V3GenClk.cpp +++ b/src/V3GenClk.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Generated Clock repairs // @@ -21,7 +20,7 @@ // GENCLK TRANSFORMATIONS: // Follow control-flow graph with assignments and var usages // ASSIGNDLY to variable later used as clock requires change detect -// +// //************************************************************************* #include "config_build.h" @@ -93,7 +92,7 @@ private: } //---- virtual void visit(AstVarRef* nodep, AstNUser*) { - // Consumption/generation of a variable, + // Consumption/generation of a variable, AstVarScope* vscp = nodep->varScopep(); if (!vscp) nodep->v3fatalSrc("Scope not assigned"); if (m_activep && !nodep->user3()) { @@ -172,7 +171,7 @@ private: //---- virtual void visit(AstVarRef* nodep, AstNUser*) { - // Consumption/generation of a variable, + // Consumption/generation of a variable, AstVarScope* vscp = nodep->varScopep(); if (!vscp) nodep->v3fatalSrc("Scope not assigned"); if (m_activep) { diff --git a/src/V3GenClk.h b/src/V3GenClk.h index 1acf35436..5a225e3de 100644 --- a/src/V3GenClk.h +++ b/src/V3GenClk.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +//-*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Generated Clock Repairs // diff --git a/src/V3Global.h b/src/V3Global.h index 4c0efedb9..9a55f457b 100644 --- a/src/V3Global.h +++ b/src/V3Global.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Common headers // diff --git a/src/V3Graph.cpp b/src/V3Graph.cpp index 66bed7ea7..5d984651f 100644 --- a/src/V3Graph.cpp +++ b/src/V3Graph.cpp @@ -1,4 +1,4 @@ -// $Id$ +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Graph optimizations // @@ -106,7 +106,7 @@ ostream& operator<<(ostream& os, V3GraphVertex* vertexp) { //###################################################################### // Edges -V3GraphEdge::V3GraphEdge(V3Graph* graphp, +V3GraphEdge::V3GraphEdge(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top, int weight, bool cutable) { UASSERT(fromp, "Null from pointer\n"); diff --git a/src/V3Graph.h b/src/V3Graph.h index 549465d82..82c09d45d 100644 --- a/src/V3Graph.h +++ b/src/V3Graph.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +//-*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Graph optimizations // @@ -67,7 +67,7 @@ public: virtual ~V3Graph(); static void debug(int level) { s_debug = level; } virtual string dotRankDir() { return "TB"; } // rankdir for dot plotting - + // METHODS void clear(); // Empty it of all vertices/edges, as if making a new object diff --git a/src/V3GraphAcyc.cpp b/src/V3GraphAcyc.cpp index 72dd5ee49..ea8f0ac06 100644 --- a/src/V3GraphAcyc.cpp +++ b/src/V3GraphAcyc.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Graph acyclic algorithm // diff --git a/src/V3GraphAlg.cpp b/src/V3GraphAlg.cpp index 0cb9b2551..7854316f4 100644 --- a/src/V3GraphAlg.cpp +++ b/src/V3GraphAlg.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Graph optimizations // @@ -345,7 +344,7 @@ private: if (m_done) return; m_callTrace.reserve(currentRank+10); // Leave slop for speed - m_callTrace[currentRank++] = vertexp; + m_callTrace[currentRank++] = vertexp; if (vertexp->user() == 1) { for (unsigned i=0; ifindStart(); - + // Create new DFA State (start state) from the NFA states DfaVertex* dfaStartp = newDfaVertex(nfaStartp); @@ -267,7 +266,7 @@ private: } } if (debug()>=6) m_graphp->dumpDotFilePrefixed("dfa_start"); - insertDfaOrigins(dfaStartp); + insertDfaOrigins(dfaStartp); int i=0; UINFO(5,"Main state conversion...\n"); @@ -293,7 +292,7 @@ private: } } } - + // Foreach input state (NFA inputs of this DFA state) for (set::const_iterator inIt=inputs.begin(); inIt!=inputs.end(); ++inIt) { DfaInput input = *inIt; @@ -303,7 +302,7 @@ private: // Find all states reachable for given input DfaStates nfasWithInput; findNfasWithInput(dfaStatep, input, nfasWithInput/*ref*/); - + // nfasWithInput now maps to the DFA we want a transition to. // Does a DFA already exist with this, and only this subset of NFA's? DfaVertex* toDfaStatep = findDfaOrigins(nfasWithInput); @@ -317,7 +316,7 @@ private: new DfaEdge (graphp(), toDfaStatep, *nfaIt, DfaEdge::NA()); if ((*nfaIt)->accepting()) toDfaStatep->accepting(true); } - insertDfaOrigins(toDfaStatep); + insertDfaOrigins(toDfaStatep); } // Add input transition new DfaEdge (graphp(), dfaStatep, toDfaStatep, input); @@ -375,7 +374,7 @@ private: } void optimize_accepting_out() { - // Delete outbound edges from accepting states + // Delete outbound edges from accepting states // (As once we've accepted, we no longer care about anything else.) for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) { if (DfaVertex* vvertexp = dynamic_cast(vertexp)) { @@ -496,7 +495,7 @@ void DfaGraph::dfaReduce() { // 2. All vertexes except start/accept get edges to NEW accept for any // non-existing case. Weedely we don't have a nice way of representing // this so we just create a edge for each case and mark it "complemented." -// +// // 3. Delete temp vertex (old accept/new reject) and related edges. // The user's old accept is now the new accept. This is imporant as // we want the virtual type of it to be intact. diff --git a/src/V3GraphDfa.h b/src/V3GraphDfa.h index 392b42571..a44d01049 100644 --- a/src/V3GraphDfa.h +++ b/src/V3GraphDfa.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Graph automata base class // @@ -46,7 +46,7 @@ class DfaEdge; /// at the end of the transformations. (If we want the complement, we /// call complement and the algorithm makes a REJECT state, then flips /// accept and reject for you.) -/// +/// /// Common transforms: /// /// "*": DfaVertex(START) --> [epsilon] -->DfaVertex(ACCEPT) @@ -87,7 +87,7 @@ public: // Vertex class DfaVertex : public V3GraphVertex { - // Each DFA state is captured in this vertex. + // Each DFA state is captured in this vertex. // Start and accepting are members, rather than the more intuitive // subclasses, as subclassing them would make it harder to inherit from here. bool m_start; // Start state diff --git a/src/V3GraphTest.cpp b/src/V3GraphTest.cpp index ced2dc8fa..8ea890959 100644 --- a/src/V3GraphTest.cpp +++ b/src/V3GraphTest.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Graph tests // @@ -112,7 +111,7 @@ public: new V3GraphEdge(gp, g1, q, 2, true); new V3GraphEdge(gp, g2, q, 2, true); new V3GraphEdge(gp, g3, q, 2, true); - + gp->stronglyConnected(&V3GraphEdge::followAlwaysTrue); dump(); @@ -143,7 +142,7 @@ public: new V3GraphEdge(gp, g1, a, 2, true); new V3GraphEdge(gp, g2, a, 2, true); new V3GraphEdge(gp, g3, a, 2, true); - + gp->acyclic(&V3GraphEdge::followAlwaysTrue); gp->order(); dump(); @@ -157,7 +156,7 @@ public: V3Graph* gp = &m_graph; V3GraphTestVertex* clk = new V3GraphTestVarVertex(gp,"$clk"); - + V3GraphTestVertex* a = new V3GraphTestVarVertex(gp,"$a"); V3GraphTestVertex* a_dly = new V3GraphTestVarVertex(gp,"$a_dly"); V3GraphTestVertex* a_dlyblk= new V3GraphTestVarVertex(gp,"$a_dlyblk"); @@ -166,13 +165,13 @@ public: V3GraphTestVertex* b_dlyblk= new V3GraphTestVarVertex(gp,"$b_dlyblk"); V3GraphTestVertex* c = new V3GraphTestVarVertex(gp,"$c"); V3GraphTestVertex* i = new V3GraphTestVarVertex(gp,"$i"); - + V3GraphTestVertex* ap = new V3GraphTestVarVertex(gp,"$a_pre"); V3GraphTestVertex* bp = new V3GraphTestVarVertex(gp,"$b_pre"); V3GraphTestVertex* cp = new V3GraphTestVarVertex(gp,"$c_pre"); - + V3GraphTestVertex* n; - + // Logical order between clk, and posedge blocks // implemented by special CLK prod/cons? // Required order between first x_DLY<=x_pre and final x<=x_DLY @@ -183,23 +182,23 @@ public: // implemented by producer/consumer on a_dly signals // Desired order between different _DLY blocks so we can elim temporaries // implemented by cutable "pre" signal dependencies - - + + n = new V3GraphTestVertex(gp,"*INPUTS*"); { new V3GraphEdge(gp, n, clk, 2); new V3GraphEdge(gp, n, i, 2); } - + V3GraphTestVertex* posedge = n = new V3GraphTestVertex(gp,"*posedge clk*"); { new V3GraphEdge(gp, clk, n, 2); } - + // AssignPre's VarRefs on LHS: generate special BLK // normal: VarRefs on LHS: generate normal // underSBlock: VarRefs on RHS: consume 'pre' (required to save cutable tests) n = new V3GraphTestVertex(gp,"a_dlyacyclic(&V3GraphEdge::followAlwaysTrue); gp->order(); @@ -288,7 +287,7 @@ public: DfaTestVertex* sr = new DfaTestVertex(gp,"sR"); DfaTestVertex* sz = new DfaTestVertex(gp,"sZ"); DfaTestVertex* sac = new DfaTestVertex(gp,"*ACCEPT*"); sac->accepting(true); - + AstNUser* L = AstNUser::fromInt(0xaa); AstNUser* R = AstNUser::fromInt(0xbb); AstNUser* Z = AstNUser::fromInt(0xcc); @@ -340,7 +339,7 @@ public: #if 0 # include "graph_export.cpp" -#else +#else void V3GraphTestImport::dotImport() { } #endif diff --git a/src/V3Hashed.cpp b/src/V3Hashed.cpp index ef82bdc39..bdd656195 100644 --- a/src/V3Hashed.cpp +++ b/src/V3Hashed.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Hashed common code into functions // @@ -19,11 +18,11 @@ // //************************************************************************* // V3Hashed's Transformations: -// +// // Hash each node depth first // Hash includes varp name and operator type, and constants // Form lookup table based on hash of each statement w/ nodep and next nodep -// +// //************************************************************************* #include "config_build.h" diff --git a/src/V3Hashed.h b/src/V3Hashed.h index 60ed96e97..b845b5463 100644 --- a/src/V3Hashed.h +++ b/src/V3Hashed.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Hash AST trees to find duplicates // diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index b84c0932c..c40e42f57 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add temporaries, such as for inline nodes // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Inline's Transformations: -// +// // Each module: // Look for CELL... PRAGMA INLINE_MODULE // Replicate the cell's module diff --git a/src/V3Inline.h b/src/V3Inline.h index a773779b6..cb4a9801e 100644 --- a/src/V3Inline.h +++ b/src/V3Inline.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Inlining of modules // diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index 4c02f31b3..500db955a 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add temporaries, such as for inst nodes // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Inst's Transformations: -// +// // Each module: // Pins: // Create a wire assign to interconnect to submodule diff --git a/src/V3Inst.h b/src/V3Inst.h index 0ae185f08..112e0e6fc 100644 --- a/src/V3Inst.h +++ b/src/V3Inst.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Break always into sensitivity inst domains // diff --git a/src/V3LanguageWords.h b/src/V3LanguageWords.h index 9dff4484d..721880567 100644 --- a/src/V3LanguageWords.h +++ b/src/V3LanguageWords.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Language rules // diff --git a/src/V3Life.cpp b/src/V3Life.cpp index de331dd2f..0ee382c70 100644 --- a/src/V3Life.cpp +++ b/src/V3Life.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Lifelicate variable assignment elimination // @@ -25,7 +24,7 @@ // We also track across if statements: // ASSIGN(X,...) IF( ..., ASSIGN(X,...), ASSIGN(X,...)) => deletes first // We don't do the opposite yet though (remove assigns in if followed by outside if) -// +// //************************************************************************* #include "config_build.h" @@ -277,7 +276,7 @@ private: // METHODS // VISITORS virtual void visit(AstVarRef* nodep, AstNUser*) { - // Consumption/generation of a variable, + // Consumption/generation of a variable, // it's used so can't elim assignment before this use. if (!nodep->varScopep()) nodep->v3fatalSrc("NULL"); // @@ -314,7 +313,7 @@ private: nodep->iterateChildren(*this); } - //---- Track control flow changes + //---- Track control flow changes virtual void visit(AstNodeIf* nodep, AstNUser*) { UINFO(4," IF "<varScopep(); if (!vscp) nodep->v3fatalSrc("Scope not assigned"); m_sequence++; diff --git a/src/V3LifePost.h b/src/V3LifePost.h index 8098cce98..ffc1d700b 100644 --- a/src/V3LifePost.h +++ b/src/V3LifePost.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Lifepost variable analysis // diff --git a/src/V3Link.cpp b/src/V3Link.cpp index 154cf1bd4..8c5a547bb 100644 --- a/src/V3Link.cpp +++ b/src/V3Link.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Resolve module/signal name references // diff --git a/src/V3Link.h b/src/V3Link.h index 9fa208769..90f828050 100644 --- a/src/V3Link.h +++ b/src/V3Link.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Link modules/signals together // diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp index 147ccfd63..7ed428a8a 100644 --- a/src/V3LinkCells.cpp +++ b/src/V3LinkCells.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Resolve module/signal name references // diff --git a/src/V3LinkCells.h b/src/V3LinkCells.h index b0d7a6cb5..6e95ea2db 100644 --- a/src/V3LinkCells.h +++ b/src/V3LinkCells.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Link modules/signals together // diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index ced34a64f..604aed677 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Resolve module/signal name references // @@ -107,7 +106,7 @@ public: class LinkDotCellVertex : public LinkDotBaseVertex { // A real point in the hierarchy, corresponding to a instantiated module - AstModule* m_modp; // Module + AstModule* m_modp; // Module AstCell* m_cellp; // Cell creating this vertex **NULL AT TOP** V3SymTable m_syms; // Symbol table of variable/task names for global lookup public: @@ -199,7 +198,7 @@ public: AstNode::user2ClearTree(); } ~LinkDotState() {} - + // ACCESSORS bool forScopeCreation() const { return m_forScopeCreation; } diff --git a/src/V3LinkDot.h b/src/V3LinkDot.h index c1c737ea8..efb22a647 100644 --- a/src/V3LinkDot.h +++ b/src/V3LinkDot.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Link XREF signals/functions together // diff --git a/src/V3LinkLValue.cpp b/src/V3LinkLValue.cpp index 1406973b0..5399b44c6 100644 --- a/src/V3LinkLValue.cpp +++ b/src/V3LinkLValue.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: LValue module/signal name references // diff --git a/src/V3LinkLValue.h b/src/V3LinkLValue.h index 37dce6489..22d4ae16a 100644 --- a/src/V3LinkLValue.h +++ b/src/V3LinkLValue.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Link modules/signals together // diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp index 7c5a28adc..6dc298fe3 100644 --- a/src/V3LinkLevel.cpp +++ b/src/V3LinkLevel.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Resolve module/signal name references // diff --git a/src/V3LinkLevel.h b/src/V3LinkLevel.h index 206cb0aa1..5a49b13a6 100644 --- a/src/V3LinkLevel.h +++ b/src/V3LinkLevel.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Link modules/signals together // diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index ac0be9ac0..321036dba 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Parse module/signal name references // diff --git a/src/V3LinkParse.h b/src/V3LinkParse.h index b98ac6be6..b5f0259ab 100644 --- a/src/V3LinkParse.h +++ b/src/V3LinkParse.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Link modules/signals together // diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index c3c8a57cd..347cb7cad 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Resolve module/signal name references // diff --git a/src/V3LinkResolve.h b/src/V3LinkResolve.h index e6ef96bee..c532fa608 100644 --- a/src/V3LinkResolve.h +++ b/src/V3LinkResolve.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Link modules/signals together // diff --git a/src/V3List.h b/src/V3List.h index d557c0372..320a92892 100644 --- a/src/V3List.h +++ b/src/V3List.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: List class with storage in existing classes // diff --git a/src/V3Localize.cpp b/src/V3Localize.cpp index 2abda56f8..a59c4d282 100644 --- a/src/V3Localize.cpp +++ b/src/V3Localize.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Convert BLOCKTEMPs to local variables // @@ -24,7 +23,7 @@ // if only referenced in a CFUNC, make it local to that CFUNC // VAR(others // if non-public, set before used, and in signle CFUNC, make it local -// +// //************************************************************************* #include "config_build.h" @@ -157,7 +156,7 @@ private: moveVars(); } virtual void visit(AstModule* nodep, AstNUser*) { - // Consumption/generation of a variable, + // Consumption/generation of a variable, nodep->iterateChildren(*this); } virtual void visit(AstCFunc* nodep, AstNUser*) { diff --git a/src/V3Localize.h b/src/V3Localize.h index f85060945..94f0eb16c 100644 --- a/src/V3Localize.h +++ b/src/V3Localize.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Convert BLOCKTEMPs to local variables // diff --git a/src/V3Name.cpp b/src/V3Name.cpp index d4875c4e5..a09aa6a0b 100644 --- a/src/V3Name.cpp +++ b/src/V3Name.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Change names for __PVT__'s // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Name's Transformations: -// +// // Cell/Var's // Prepend __PVT__ to variable names //************************************************************************* diff --git a/src/V3Name.h b/src/V3Name.h index 6b26711c0..7b62bfcaf 100644 --- a/src/V3Name.h +++ b/src/V3Name.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Change names for inlining // diff --git a/src/V3Number.cpp b/src/V3Number.cpp index 97084d750..4cdb33b67 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Large 4-state numbers // @@ -97,7 +96,7 @@ V3Number::V3Number (FileLine* fileline, const char* sourcep) { unbased = true; base = 'd'; } - + for (int i=0; iwidth(); bit++) { - if (bitIs1(bit)) n++; + if (bitIs1(bit)) n++; } return n; } @@ -845,7 +844,7 @@ last: V3Number& V3Number::opWildNeq (const V3Number& lhs, const V3Number& rhs) { char outc = 0; for (int bit=0; bitinsert(direntp->d_name); } closedir(dirp); @@ -268,7 +267,7 @@ void V3Options::unlinkRegexp(const string& dir, const string& regexp) { closedir(dirp); } } - + //###################################################################### // Environment @@ -409,7 +408,7 @@ string V3Options::downcase(const string& str) { string V3Options::version() { string ver = DTVERSION; - ver += " rev"+cvtToStr(DTVERSION_rev); + ver += " rev "+cvtToStr(DTVERSION_rev); #ifdef NEW_ORDERING ver += " (ord)"; #endif @@ -741,7 +740,7 @@ void V3Options::parseOptsFile(FileLine* fl, const string& filename) { if (*pos=='*' && *(pos+1)=='/') { inCmt = false; pos++; - } + } } else if (*pos=='/' && *(pos+1)=='/') { break; // Ignore to EOL } else if (*pos=='/' && *(pos+1)=='*') { diff --git a/src/V3Options.h b/src/V3Options.h index b94864d56..1d73d60ff 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Command line options // diff --git a/src/V3Order.cpp b/src/V3Order.cpp index a3ee912c4..2ea789324 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Block code ordering // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Order's Transformations: -// +// // Compute near optimal scheduling of always/wire statements // Make a graph of the entire netlist // @@ -30,8 +29,8 @@ // // For seq logic // Add logic_sensitive_vertex for this list of SenItems -// Add edge for each sensitive_var->logic_sensitive_vertex -// For AssignPre's +// Add edge for each sensitive_var->logic_sensitive_vertex +// For AssignPre's // Add vertex for this logic // Add edge logic_sensitive_vertex->logic_vertex // Add edge logic_consumed_var_PREVAR->logic_vertex @@ -189,7 +188,7 @@ inline ostream& operator<< (ostream& lhs, const OrderMoveDomScope& rhs) { //###################################################################### // Order information stored under each AstNode::userp()... - + // Types of vertex we can create enum WhichVertex { WV_STD, WV_PRE, WV_PORD, WV_POST, WV_SETL, WV_MAX}; @@ -223,7 +222,7 @@ public: return vertexp; } -public: +public: // CONSTRUCTORS OrderUser() { for (int i=0; iinBeginp(); edgep; edgep = nextp) { nextp = edgep->inNextp(); // Func may edit the list - if (edgep->weight()) { + if (edgep->weight()) { processInsLoopEdge(edgep); } else { // No purpose to this edge any longer edgep->unlinkDelete(); edgep=NULL; // remove old edge diff --git a/src/V3Order.h b/src/V3Order.h index d867df864..47c4066cd 100644 --- a/src/V3Order.h +++ b/src/V3Order.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Block code ordering // diff --git a/src/V3OrderGraph.h b/src/V3OrderGraph.h index 8ab748dd4..c44e78f10 100644 --- a/src/V3OrderGraph.h +++ b/src/V3OrderGraph.h @@ -1,4 +1,4 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Block code ordering // @@ -256,7 +256,7 @@ public: //--- Looping constructs class OrderLoopBeginVertex : public OrderLogicVertex { - // A vertex can never be under two loops... + // A vertex can never be under two loops... // However, a LoopBeginVertex is not "under" the loop per se, and it may be under another loop. OrderLoopId m_loopId; // Arbitrary # to ID this loop uint32_t m_loopColor; // Color # of loop (for debug) @@ -389,7 +389,7 @@ public: class OrderComboCutEdge : public OrderEdge { // Edge created from output of combo logic // Breakable if the output var is also a input, - // in which case we'll need a change detect loop around this var. + // in which case we'll need a change detect loop around this var. public: OrderComboCutEdge(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top) : OrderEdge(graphp, fromp, top, WEIGHT_COMBO, CUTABLE) {} @@ -406,7 +406,7 @@ public: class OrderPostCutEdge : public OrderEdge { // Edge created from output of post assignment // Breakable if the output var feeds back to input combo logic or another clock pin - // in which case we'll need a change detect loop around this var. + // in which case we'll need a change detect loop around this var. public: OrderPostCutEdge(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top) : OrderEdge(graphp, fromp, top, WEIGHT_COMBO, CUTABLE) {} diff --git a/src/V3Param.cpp b/src/V3Param.cpp index d285e4779..fb42d7be1 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Replicate modules for parameterization // @@ -230,7 +229,7 @@ public: void ParamVisitor::visit(AstCell* nodep, AstNUser*) { // Cell: Check for parameters in the instantiation. if (!nodep->modp()) { nodep->dumpTree(cout,"error:"); nodep->v3fatalSrc("Not linked?"); } - if (nodep->paramsp()) { + if (nodep->paramsp()) { UINFO(4,"De-parameterize: "<9) nodep->dumpTree(cout,"cell:\t"); @@ -336,7 +335,7 @@ void ParamVisitor::visit(AstCell* nodep, AstNUser*) { nodep->paramsp()->unlinkFrBackWithNext(&delHandle); delHandle.oldp()->deleteTree(); } - + // We need to relink the pins to the new module VarCloneMap* clonemapp = &(iter->second.m_cloneMap); relinkPins(clonemapp, nodep->pinsp()); diff --git a/src/V3Param.h b/src/V3Param.h index 73caf0fc1..925fe5087 100644 --- a/src/V3Param.h +++ b/src/V3Param.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Param modules/signals together // diff --git a/src/V3Parse.cpp b/src/V3Parse.cpp index 69a708c99..71b8c2a06 100644 --- a/src/V3Parse.cpp +++ b/src/V3Parse.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Parse syntax tree // diff --git a/src/V3PreLex.h b/src/V3PreLex.h index d65094cbb..eebf9620c 100644 --- a/src/V3PreLex.h +++ b/src/V3PreLex.h @@ -1,4 +1,4 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilog::Preproc: Internal header for lex interfacing // diff --git a/src/V3PreLex.l b/src/V3PreLex.l index acc0b18cd..4dbfd6e4a 100644 --- a/src/V3PreLex.l +++ b/src/V3PreLex.l @@ -1,4 +1,4 @@ -/* $Id$ -*- C++ -*- */ +/* -*- C++ -*- */ /************************************************************************** * DESCRIPTION: Verilator: Flex verilog preprocessor * @@ -148,7 +148,7 @@ psl [p]sl [(] { V3PreLex::s_currentLexp->m_parenLevel++; // Note paren level 0 means before "(" of starting args // Level 1 means "," between arguments - // Level 2+ means one argument's internal () + // Level 2+ means one argument's internal () if (V3PreLex::s_currentLexp->m_parenLevel>1) { appendDefValue(yytext,yyleng); } else { diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index 3d835ec97..79b96c668 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -1,4 +1,4 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilog::Preproc: Internal implementation of default preprocessor // @@ -69,7 +69,7 @@ class V3DefineRef { string m_params; // Define parameter list for next expansion string m_nextarg; // String being built for next argument int m_parenLevel; // Parenthesis counting inside def args - + vector m_args; // List of define arguments public: string name() const { return m_name; } @@ -366,21 +366,21 @@ const char* V3PreProcImp::tokenName(int tok) { case VP_ENDIF : return("ENDIF"); case VP_UNDEF : return("UNDEF"); case VP_DEFINE : return("DEFINE"); - case VP_ELSE : return("ELSE"); - case VP_ELSIF : return("ELSIF"); - case VP_LINE : return("LINE"); + case VP_ELSE : return("ELSE"); + case VP_ELSIF : return("ELSIF"); + case VP_LINE : return("LINE"); case VP_SYMBOL : return("SYMBOL"); case VP_STRING : return("STRING"); case VP_DEFVALUE : return("DEFVALUE"); case VP_COMMENT : return("COMMENT"); - case VP_TEXT : return("TEXT"); - case VP_WHITE : return("WHITE"); + case VP_TEXT : return("TEXT"); + case VP_WHITE : return("WHITE"); case VP_DEFREF : return("DEFREF"); case VP_DEFARG : return("DEFARG"); case VP_ERROR : return("ERROR"); case VP_PSL : return("PSL"); default: return("?"); - } + } } string V3PreProcImp::trimWhitespace(const string& strg) { @@ -593,7 +593,7 @@ int V3PreProcImp::getRawToken() { if (yyleng) m_rawAtBol = (yytext[yyleng-1]=='\n'); if (m_state!=ps_DEFVALUE) return (VP_TEXT); else { - V3PreLex::s_currentLexp->appendDefValue(yytext,yyleng); + V3PreLex::s_currentLexp->appendDefValue(yytext,yyleng); goto next_tok; } } @@ -613,7 +613,7 @@ int V3PreProcImp::getRawToken() { fileline()->lineno(), m_off?"of":"on", m_state, (int)m_defRefs.size(), tokenName(tok), buf.c_str()); } - + // On EOF, try to pop to upper level includes, as needed. if (tok==VP_EOF) { eof(); @@ -753,7 +753,7 @@ int V3PreProcImp::getToken() { // DEFVALUE is terminated by a return, but lex can't return both tokens. // Thus, we emit a return here. yytext=(char*)(newlines.c_str()); yyleng=newlines.length(); - return(VP_WHITE); + return(VP_WHITE); } case ps_DEFPAREN: { if (tok==VP_TEXT && yyleng==1 && yytext[0]=='(') { diff --git a/src/V3PreProc.h b/src/V3PreProc.h index 6905bfe55..45d31d74b 100644 --- a/src/V3PreProc.h +++ b/src/V3PreProc.h @@ -1,4 +1,4 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilog::Preproc: Preprocess verilog code // diff --git a/src/V3PreShell.cpp b/src/V3PreShell.cpp index 1c24e6825..8c37ad86c 100644 --- a/src/V3PreShell.cpp +++ b/src/V3PreShell.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Preprocessing wrapper // diff --git a/src/V3PreShell.h b/src/V3PreShell.h index c73f0d5de..98407a9e7 100644 --- a/src/V3PreShell.h +++ b/src/V3PreShell.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Preprocessing wrapper program // diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp index 33f5b9c52..28ad08e96 100644 --- a/src/V3Premit.cpp +++ b/src/V3Premit.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add temporaries, such as for premit nodes // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Premit's Transformations: -// +// // Each module: // For each wide OP, make a a temporary variable with the wide value // For each deep expression, assign expression to temporary. diff --git a/src/V3Premit.h b/src/V3Premit.h index b0fc36fad..90f1c57e9 100644 --- a/src/V3Premit.h +++ b/src/V3Premit.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Pre C-Emit stage changes // diff --git a/src/V3Read.cpp b/src/V3Read.cpp index 28dfd5c49..98db6fa91 100644 --- a/src/V3Read.cpp +++ b/src/V3Read.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Netlist (top level) functions // diff --git a/src/V3Read.h b/src/V3Read.h index 4b33868ef..0af75f6c6 100644 --- a/src/V3Read.h +++ b/src/V3Read.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Reading of Verilog files // diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp index 0b58ff068..8c32bec5b 100644 --- a/src/V3Scope.cpp +++ b/src/V3Scope.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Break always into sensitivity block domains // @@ -19,11 +18,11 @@ // //************************************************************************* // V3Scope's Transformations: -// -// For every CELL that references this module, create a +// +// For every CELL that references this module, create a // SCOPE // {all blocked statements} -// +// //************************************************************************* #include "config_build.h" @@ -56,7 +55,7 @@ private: AstScope* m_aboveScopep; // Scope that instantiates this scope //int debug() { return 9; } - + // VISITORS virtual void visit(AstNetlist* nodep, AstNUser*) { AstModule* modp = nodep->topModulep(); @@ -74,7 +73,7 @@ private: UINFO(4," MOD AT "<fileline(), nodep, scopename, m_aboveScopep, m_aboveCellp); diff --git a/src/V3Scope.h b/src/V3Scope.h index bf4fe5790..643f2466e 100644 --- a/src/V3Scope.h +++ b/src/V3Scope.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Break always into sensitivity block domains // diff --git a/src/V3SenTree.h b/src/V3SenTree.h index 13c27c88e..87c61e820 100644 --- a/src/V3SenTree.h +++ b/src/V3SenTree.h @@ -1,4 +1,4 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Break always into sensitivity block domains // @@ -19,7 +19,7 @@ // //************************************************************************* // V3Block's Transformations: -// +// // Note this can be called multiple times. // Create a IBLOCK(initial), SBLOCK(combo) // ALWAYS: Remove any-edges from sense list @@ -87,7 +87,7 @@ private: // METHODS public: void clear() { - m_topscopep = NULL; + m_topscopep = NULL; m_treesp.clear(); } AstSenTree* getSenTree(FileLine* fl, AstSenTree* sensesp) { diff --git a/src/V3Signed.cpp b/src/V3Signed.cpp index e817277b6..2468703c6 100644 --- a/src/V3Signed.cpp +++ b/src/V3Signed.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Signed/unsigned resolution // @@ -225,7 +224,7 @@ private: } // These have different node types, as they operate differently - // Must add to case statement below, + // Must add to case statement below, virtual void visit(AstGt* nodep, AstNUser*) { checkReplace_Ou_FlavLhsAndRhs(nodep); } virtual void visit(AstGtS* nodep, AstNUser*) { checkReplace_Ou_FlavLhsAndRhs(nodep); } virtual void visit(AstGte* nodep, AstNUser*) { checkReplace_Ou_FlavLhsAndRhs(nodep); } diff --git a/src/V3Signed.h b/src/V3Signed.h index 530d6bf55..f633a5a0c 100644 --- a/src/V3Signed.h +++ b/src/V3Signed.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Signed/unsigned resolution // diff --git a/src/V3Split.cpp b/src/V3Split.cpp index ea3ab232e..58f6d1e4b 100644 --- a/src/V3Split.cpp +++ b/src/V3Split.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Break always into separate statements to reduce temps // diff --git a/src/V3Split.h b/src/V3Split.h index b0f43573a..e586dc434 100644 --- a/src/V3Split.h +++ b/src/V3Split.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Break always into separate statements to reduce temps // diff --git a/src/V3SplitAs.cpp b/src/V3SplitAs.cpp index 714f2d9cf..b8472e1a8 100644 --- a/src/V3SplitAs.cpp +++ b/src/V3SplitAs.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Break always into separate statements to reduce temps // diff --git a/src/V3SplitAs.h b/src/V3SplitAs.h index bab9aa6e8..4a6194ffe 100644 --- a/src/V3SplitAs.h +++ b/src/V3SplitAs.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Break always into separate statements to reduce temps // diff --git a/src/V3Stats.cpp b/src/V3Stats.cpp index f691f460b..666e583e5 100644 --- a/src/V3Stats.cpp +++ b/src/V3Stats.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Collect and print statistics // @@ -46,7 +45,7 @@ private: V3Double0 m_statInstrLong; // Instruction count bool m_counting; // Currently counting double m_instrs; // Current instr count - + vector m_statTypeCount; // Nodes of given type V3Double0 m_statAbove[AstType::_ENUM_END][AstType::_ENUM_END]; // Nodes of given type V3Double0 m_statPred[AstBranchPred::_ENUM_END]; // Nodes of given type diff --git a/src/V3Stats.h b/src/V3Stats.h index e682b4382..4e53b4307 100644 --- a/src/V3Stats.h +++ b/src/V3Stats.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Collect and print statistics // diff --git a/src/V3StatsReport.cpp b/src/V3StatsReport.cpp index 312f5c0f4..1ad59b89f 100644 --- a/src/V3StatsReport.cpp +++ b/src/V3StatsReport.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Collect and print statistics // diff --git a/src/V3Subst.cpp b/src/V3Subst.cpp index f43e554c0..ffc2bde2a 100644 --- a/src/V3Subst.cpp +++ b/src/V3Subst.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Substitute constants and expressions in expr temp's // diff --git a/src/V3Subst.h b/src/V3Subst.h index 8040017a7..35e17c1f0 100644 --- a/src/V3Subst.h +++ b/src/V3Subst.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Substitute constants and expressions in expr temp's // diff --git a/src/V3SymTable.h b/src/V3SymTable.h index cee7d52c3..dd5c02ea3 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Symbol table // diff --git a/src/V3Table.cpp b/src/V3Table.cpp index 14b16d020..dd87348de 100644 --- a/src/V3Table.cpp +++ b/src/V3Table.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Make lookup tables // diff --git a/src/V3Table.h b/src/V3Table.h index aa0d45615..4d5e1e9b0 100644 --- a/src/V3Table.h +++ b/src/V3Table.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Make lookup tables // diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 580ea4995..d23ac1adb 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add temporaries, such as for task nodes // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Task's Transformations: -// +// // Each module: // Look for TASKREF // Insert task's statements into the referrer @@ -553,7 +552,7 @@ private: AstNode* bodysp = nodep->stmtsp(); if (bodysp) { bodysp->unlinkFrBackWithNext(); cfuncp->addStmtsp(bodysp); } // Return statement - if (rtnvscp && forUser) { + if (rtnvscp && forUser) { cfuncp->addFinalsp(new AstCReturn(rtnvscp->fileline(), new AstVarRef(rtnvscp->fileline(), rtnvscp, false))); } diff --git a/src/V3Task.h b/src/V3Task.h index b8e94a431..a3cf06ea4 100644 --- a/src/V3Task.h +++ b/src/V3Task.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Inlining of modules // diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp index e485c4e6c..190ae0a14 100644 --- a/src/V3Trace.cpp +++ b/src/V3Trace.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Waves tracing // @@ -44,7 +43,7 @@ // Assign trace codes: // If from a VARSCOPE, record the trace->varscope map // Else, assign trace codes to each variable -// +// //************************************************************************* #include "config_build.h" @@ -155,7 +154,7 @@ private: // NODE STATE // V3Hashed // Ast*::user4() // V3Hashed calculation - // Cleared entire netlist + // Cleared entire netlist // AstCFunc::user() // V3GraphVertex* for this node // AstTraceInc::user() // V3GraphVertex* for this node // AstVarScope::user() // V3GraphVertex* for this node diff --git a/src/V3Trace.h b/src/V3Trace.h index 96f055236..a8946b322 100644 --- a/src/V3Trace.h +++ b/src/V3Trace.h @@ -1,6 +1,6 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* -// DESCRIPTION: Verilator: Waves Tracing +// DESCRIPTION: Verilator: Waves Tracing // // Code available from: http://www.veripool.org/verilator // diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index f67dc9029..3f60ffc2d 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Waves tracing // @@ -22,7 +21,7 @@ // Create trace CFUNCs // For each VARSCOPE // If appropriate type of signal, create a TRACE -// +// //************************************************************************* #include "config_build.h" @@ -42,7 +41,7 @@ class TraceDeclVisitor : public EmitCBaseVisitor { private: // NODE STATE - // Cleared entire netlist + // Cleared entire netlist // STATE AstModule* m_modp; // Current module diff --git a/src/V3TraceDecl.h b/src/V3TraceDecl.h index 491106655..40d5ecec5 100644 --- a/src/V3TraceDecl.h +++ b/src/V3TraceDecl.h @@ -1,6 +1,6 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* -// DESCRIPTION: Verilator: Waves Tracing +// DESCRIPTION: Verilator: Waves Tracing // // Code available from: http://www.veripool.org/verilator // diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index 378279d9b..826d4d5f5 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add Unknown assigns // @@ -19,7 +18,7 @@ // //************************************************************************* // V3Unknown's Transformations: -// +// // Each module: // TBD: Eliminate tristates by adding __in, __inen, __en wires in parallel // Need __en in changed list if a signal is on the LHS of a assign @@ -270,7 +269,7 @@ private: // Link in conditional, can blow away temp xor AstNode* nnp = newp->lhsp()->unlinkFrBack(); replaceHandle.relink(nnp); nodep=NULL; - newp->deleteTree(); newp=NULL; + newp->deleteTree(); newp=NULL; // Added X's, tristate them too nnp->accept(*this); } @@ -341,7 +340,7 @@ private: // Link in conditional, can blow away temp xor AstNode* nnp = newp->lhsp()->unlinkFrBack(); replaceHandle.relink(nnp); nodep=NULL; - newp->deleteTree(); newp=NULL; + newp->deleteTree(); newp=NULL; // Added X's, tristate them too nnp->accept(*this); } diff --git a/src/V3Unknown.h b/src/V3Unknown.h index 4f50d7065..20b4df8ae 100644 --- a/src/V3Unknown.h +++ b/src/V3Unknown.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Add Unknown assigns // diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp index cd52f2cd5..a493b4645 100644 --- a/src/V3Unroll.cpp +++ b/src/V3Unroll.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: Add temporaries, such as for unroll nodes // @@ -21,7 +20,7 @@ // V3Unroll's Transformations: // Note is called twice. Once on modules for GenFor unrolling, // Again after V3Scope for normal for loop unrolling. -// +// // Each module: // Look for "FOR" loops and unroll them if <= 32 loops. // (Eventually, a better way would be to simulate the entire loop; ala V3Table.) @@ -361,7 +360,7 @@ private: && nodep->varp() == m_forVarp && nodep->varScopep() == m_forVscp && nodep->lvalue()) { - UINFO(8," Itervar assigned to: "<msbConst()<<"<"<lsbConst()); width = (nodep->lsbConst() - nodep->msbConst() + 1); nodep->width(width,width); - nodep->widthp()->replaceWith(new AstConst(nodep->widthp()->fileline(), + nodep->widthp()->replaceWith(new AstConst(nodep->widthp()->fileline(), width)); nodep->lsbp()->replaceWith(new AstConst(nodep->lsbp()->fileline(), 0)); } @@ -327,7 +326,7 @@ private: int fromlsb; if (!varrp->varp()->arrayp(dimension)) { nodep->v3fatalSrc("Array reference exceeds dimension of array"); - } + } if (1) { // ARRAY slice extraction int outwidth = varrp->width(); // Width of variable frommsb = varrp->varp()->arrayp(dimension)->msbConst(); diff --git a/src/V3Width.h b/src/V3Width.h index 84d60cc0a..ebd7d1604 100644 --- a/src/V3Width.h +++ b/src/V3Width.h @@ -1,4 +1,4 @@ -// $Id$ //-*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Node attributes/ expression widths // diff --git a/src/Verilator.cpp b/src/Verilator.cpp index b12480547..e3854eeff 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -1,4 +1,3 @@ -// $Id$ //************************************************************************* // DESCRIPTION: Verilator: main() // @@ -235,7 +234,7 @@ void process () { v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("scope.tree")); V3LinkDot::linkDotScope(v3Global.rootp()); v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("linkdot.tree")); - + //--SCOPE BASED OPTIMIZATIONS-------------- // Cleanup @@ -459,7 +458,7 @@ void process () { // Add C casts when longs need to become long-long and vice-versa // Note depth may insert something needing a cast, so this must be last. V3Cast::castAll(v3Global.rootp()); - v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("cast.tree")); + v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("cast.tree")); } V3Error::abortIfErrors(); @@ -554,7 +553,7 @@ int main(int argc, char** argv, char** env) { V3File::writeDepend(v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__ver.d"); } if (!v3Global.opt.lintOnly() - && (v3Global.opt.skipIdentical() || v3Global.opt.makeDepend())) { + && (v3Global.opt.skipIdentical() || v3Global.opt.makeDepend())) { V3File::writeTimes(v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__verFiles.dat", argString); } @@ -563,6 +562,6 @@ int main(int argc, char** argv, char** env) { v3Global.clear(); #endif FileLine::deleteAllRemaining(); - + UINFO(1,"Done, Exiting...\n"); } diff --git a/src/astgen b/src/astgen index 05d1e60f2..e50a5a8e8 100755 --- a/src/astgen +++ b/src/astgen @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -#$Id$ ###################################################################### # # Copyright 2002-2008 by Wilson Snyder. @@ -7,16 +6,16 @@ # This program is free software; you can redistribute it and/or modify # it under the terms of either the GNU General Public License or the # Perl Artistic License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the Perl Artistic License # along with this module; see the file COPYING. If not, see # www.cpan.org -# +# ###################################################################### #require 5.006_001; @@ -53,13 +52,12 @@ if ($opt_classes) { write_types("V3Ast__gen_types.h"); } foreach my $cpt (@Opt_Cpt) { - Cpt::process(in_filename=>"$Opt_I[0]/${cpt}.cpp", out_filename=>"${cpt}__gen.cpp"); + Cpt::process(in_filename=>"$Opt_I[0]/${cpt}.cpp", out_filename=>"${cpt}__gen.cpp"); } #---------------------------------------------------------------------- sub usage { - print '$Id$ ', "\n"; pod2usage(-verbose=>2, -exitval => 2); exit (1); } @@ -78,7 +76,7 @@ sub parameter { die "%Error: Unknown parameter: $param,"; } } - + ####################################################################### sub read_types { @@ -238,7 +236,7 @@ sub process { my $fhi = IO::File->new($self->{in_filename}) or die "%Error: $! $self->{in_filename},"; while (defined(my $line = $fhi->getline)) { if (!$didln) { - $self->print("#line $. \"$self->{in_filename}\"\n"); + $self->print("#line $. \"$self->{in_filename}\"\n"); $didln = 1; } if ($line =~ /^\s+(TREE.*)$/) { @@ -259,7 +257,7 @@ sub process { } $fhi->close; - # Put out the resultant file, if the list has a reference to a + # Put out the resultant file, if the list has a reference to a # function, then call that func to generate output my $fho = ::open_file($self->{out_filename}); my @togen = @{$self->{out_lines}}; @@ -281,7 +279,7 @@ sub process { sub tree_line { my $self = shift; my $func = shift; - + $func =~ s!\s*//.*$!!; $func =~ s!\s*;\s*$!!; @@ -384,7 +382,7 @@ sub treeop_exec_func { my $nargs = 0; my %argnums; # Number for each argument name - + my $aref = undef; # Recursive array with structure to form my @astack; my $forming = ""; @@ -468,7 +466,7 @@ sub tree_base { foreach my $type (sort (keys %::Classes)) { my $base = $::Classes{$type}; my @out_for_type; - foreach my $base (::subclasses_of($type), $type) { + foreach my $base (::subclasses_of($type), $type) { foreach my $typefunc (@{$self->{treeop}{$base}}) { my @lines = (" if ($typefunc->{match_func}(nodep)) return;\n",); if ($typefunc->{order}) { diff --git a/src/bisonfix b/src/bisonfix index 81eaf5b89..1c83e08ac 100755 --- a/src/bisonfix +++ b/src/bisonfix @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -#$Id$ ###################################################################### # # Copyright 2008-2008 by Wilson Snyder. @@ -7,16 +6,16 @@ # This program is free software; you can redistribute it and/or modify # it under the terms of either the GNU General Public License or the # Perl Artistic License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the Perl Artistic License # along with this module; see the file COPYING. If not, see # www.cpan.org -# +# ###################################################################### # DESCRIPTION: Edits bison output to get around various issues. diff --git a/src/config_build.h.in b/src/config_build.h.in index 56b80a999..b52788fb7 100644 --- a/src/config_build.h.in +++ b/src/config_build.h.in @@ -1,8 +1,8 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Configure source; system configuration // -// This file is part of Verilator. +// This file is part of Verilator. // // Author: Wilson Snyder // @@ -18,7 +18,7 @@ // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. -// +// //************************************************************************* //********************************************************************** diff --git a/src/config_rev.pl b/src/config_rev.pl index f38a7c46c..5fa77ec57 100755 --- a/src/config_rev.pl +++ b/src/config_rev.pl @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -#$Id$ ###################################################################### # # Copyright 2005-2008 by Wilson Snyder. @@ -7,16 +6,16 @@ # This program is free software; you can redistribute it and/or modify # it under the terms of either the GNU General Public License or the # Perl Artistic License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the Perl Artistic License # along with this module; see the file COPYING. If not, see # www.cpan.org -# +# ###################################################################### # DESCRIPTION: Query's subversion to get version number @@ -24,9 +23,15 @@ my $dir = $ARGV[0]; defined $dir or die "%Error: No directory argument,"; chdir $dir; -my $data = `svn info`; -if ($data !~ /\nRevision:\s*(\d+)/) { - die "%Error: No svn info revision found,"; +my $data = `git log | head -1`; +if ($data !~ /commit\s*([a-z0-9]+)/i) { + die "%Error: No git revision found,"; } my $rev = $1; -print "static int DTVERSION_rev = $rev;\n"; + +$data = `git status`; +if ($data !~ /nothing to commit/i) { + $rev .= " (mod)"; +} + +print "static const char* DTVERSION_rev = \"$rev\";\n"; diff --git a/src/flexfix b/src/flexfix index 7837a10ec..f3bafe04a 100755 --- a/src/flexfix +++ b/src/flexfix @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -#$Id$ ###################################################################### # # Copyright 2002-2008 by Wilson Snyder. @@ -7,16 +6,16 @@ # This program is free software; you can redistribute it and/or modify # it under the terms of either the GNU General Public License or the # Perl Artistic License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the Perl Artistic License # along with this module; see the file COPYING. If not, see # www.cpan.org -# +# ###################################################################### # DESCRIPTION: Edits flex output to get around various broken flex issues. diff --git a/src/verilog.l b/src/verilog.l index d91d0c9aa..bdeaa3f52 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -1,4 +1,4 @@ -/* $Id$ -*- C++ -*- */ +/* -*- C++ -*- */ /************************************************************************** * DESCRIPTION: Verilator: Flex input file * @@ -20,7 +20,6 @@ %option interactive c++ stack noyywrap %{ /* %option nodefault */ -/* $Id$ */ #include #include @@ -699,7 +698,7 @@ escid \\[^ \t\f\r\n]+ /************************************************************************/ /* Attributes */ \n { yymore(); NEXTLINE(); } -"*)" { yy_pop_state(); } +"*)" { yy_pop_state(); } . { yymore(); } <> { yyerrorf("EOF in (*"); yyleng = 0; yy_pop_state(); } diff --git a/src/verilog.y b/src/verilog.y index 32ae978c1..c01a707cf 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1,4 +1,4 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- //************************************************************************* // DESCRIPTION: Verilator: Bison grammer file // @@ -20,7 +20,6 @@ //************************************************************************* %{ -/* $Id$ */ #include #include #include @@ -518,7 +517,7 @@ portV2kSecond: portV2kDecl { $$ = $1; } ; portV2kInit: portV2kSig { $$=$1; } - | portV2kSig '=' expr + | portV2kSig '=' expr { $$=$1; $$->addNext(new AstInitial($2,new AstAssign($2, new AstVarRef($2,V3Parse::s_varAttrp->name(),true), $3))); } ; diff --git a/test_c/.cvsignore b/test_c/.gitignore similarity index 100% rename from test_c/.cvsignore rename to test_c/.gitignore diff --git a/test_c/Makefile b/test_c/Makefile index 6fc924f04..b31fc373b 100644 --- a/test_c/Makefile +++ b/test_c/Makefile @@ -1,4 +1,3 @@ -# $Id$ #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside source directory @@ -21,7 +20,7 @@ export VERILATOR_ROOT # Pick up PERL and other variable settings include $(VERILATOR_ROOT)/include/verilated.mk -DEBUG_ON = --debug --trace-dups +DEBUG_ON = --debug --trace-dups #DEBUG = $(DEBUG_ON) VALGRIND_ON = $(DEBUG_ON) --gdb "valgrind -v --leak-check=yes" @@ -44,7 +43,7 @@ prep_vg: compile: cd obj_dir ; $(MAKE) -j 3 -f ../Makefile_obj -run: +run: obj_dir/simx ###################################################################### diff --git a/test_c/Makefile_obj b/test_c/Makefile_obj index 3b3bca54f..e34bb6e89 100644 --- a/test_c/Makefile_obj +++ b/test_c/Makefile_obj @@ -1,4 +1,4 @@ -# $Id$ -*- Makefile -*- +# -*- Makefile -*- #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside object directory diff --git a/test_c/sim_main.cpp b/test_c/sim_main.cpp index 309212c40..3ccf0ce90 100644 --- a/test_c/sim_main.cpp +++ b/test_c/sim_main.cpp @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator Example: Top level main for invoking model // // Copyright 2003-2008 by Wilson Snyder. This program is free software; you can @@ -11,7 +10,7 @@ # include // Trace file format header (from SystemPerl) #endif -Vtop *top; // Instantiation of module +Vtop *top; // Instantiation of module unsigned int main_time = 0; // Current simulation time @@ -42,10 +41,10 @@ int main(int argc, char **argv, char **env) { if ((main_time % 10) == 3) { // Toggle clock top->clk = 1; - } + } if ((main_time % 10) == 8) { top->clk = 0; - } + } if (main_time > 10) { top->reset_l = 1; // Deassert reset } else if (main_time > 1) { diff --git a/test_regress/.cvsignore b/test_regress/.gitignore similarity index 100% rename from test_regress/.cvsignore rename to test_regress/.gitignore diff --git a/test_regress/Makefile b/test_regress/Makefile index dd7e1a52b..26bb85c90 100644 --- a/test_regress/Makefile +++ b/test_regress/Makefile @@ -1,4 +1,3 @@ -# $Id$ */ #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside source directory diff --git a/test_regress/Makefile_obj b/test_regress/Makefile_obj index 0adb9cf0c..7a783f03e 100644 --- a/test_regress/Makefile_obj +++ b/test_regress/Makefile_obj @@ -1,4 +1,4 @@ -# $Id$ -*- Makefile -*- +# -*- Makefile -*- #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside object directory @@ -24,7 +24,7 @@ include $(VM_PREFIX).mk ifeq ($(VERILATOR_AUTHOR_SITE),1) #OBJCACHE := objcache --read --write -#OBJCACHE_HOSTS := +#OBJCACHE_HOSTS := endif ####################################################################### diff --git a/test_regress/driver.pl b/test_regress/driver.pl index d3219c408..08ce5d6ab 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -# $Id$ ###################################################################### # # This program is Copyright 2003-2008 by Wilson Snyder. @@ -7,12 +6,12 @@ # This program is free software; you can redistribute it and/or modify # it under the terms of either the GNU General Public License or the # Perl Artistic License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# ###################################################################### require 5.006_001; @@ -148,7 +147,6 @@ exit(10) if $failcnt; #---------------------------------------------------------------------- sub usage { - print '$Id$ ', "\n"; pod2usage(-verbose=>2, -exitval => 2); exit (1); } @@ -165,7 +163,7 @@ sub parameter { die "%Error: Unknown parameter: $param\n"; } } - + ####################################################################### ####################################################################### ####################################################################### @@ -538,7 +536,7 @@ sub _make_main { my $VM_PREFIX = $self->{VM_PREFIX}; print $fh "#include \"$VM_PREFIX.h\"\n"; - + print $fh "// Compile in-place for speed\n"; print $fh "#include \"verilated.cpp\"\n"; print $fh "#include \"systemc.h\"\n" if $self->sc; diff --git a/test_regress/input.vc b/test_regress/input.vc index 7716927ed..6fb08696b 100644 --- a/test_regress/input.vc +++ b/test_regress/input.vc @@ -1,9 +1,8 @@ -+librescan +libext+.v ++librescan +libext+.v -y t -y obj_dir/ +incdir+t +incdir+../include +incdir+obj_dir/ - \ No newline at end of file diff --git a/test_regress/t/t_EXAMPLE.pl b/test_regress/t/t_EXAMPLE.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_EXAMPLE.pl +++ b/test_regress/t/t_EXAMPLE.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v index 378ef653e..e67a19f5e 100644 --- a/test_regress/t/t_EXAMPLE.v +++ b/test_regress/t/t_EXAMPLE.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // Use this file as a template for submitting bugs, etc. @@ -88,7 +87,7 @@ module Test (/*AUTOARG*/ // merge the output values into the result vector. input clk; - input [31:0] in; + input [31:0] in; output [31:0] out; /*AUTOREG*/ diff --git a/test_regress/t/t_alw_combdly.pl b/test_regress/t/t_alw_combdly.pl index eff491d7a..2b6dd79c0 100755 --- a/test_regress/t/t_alw_combdly.pl +++ b/test_regress/t/t_alw_combdly.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_alw_combdly.v b/test_regress/t/t_alw_combdly.v index c211a1625..08487611c 100644 --- a/test_regress/t/t_alw_combdly.v +++ b/test_regress/t/t_alw_combdly.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_alw_dly.pl b/test_regress/t/t_alw_dly.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_alw_dly.pl +++ b/test_regress/t/t_alw_dly.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_alw_dly.v b/test_regress/t/t_alw_dly.v index 1b57f0ac6..781a6706c 100644 --- a/test_regress/t/t_alw_dly.v +++ b/test_regress/t/t_alw_dly.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_alw_split.pl b/test_regress/t/t_alw_split.pl index b50e64cb2..85ca4f135 100755 --- a/test_regress/t/t_alw_split.pl +++ b/test_regress/t/t_alw_split.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_alw_split.v b/test_regress/t/t_alw_split.v index 02ad8bd8e..6f46c27ed 100644 --- a/test_regress/t/t_alw_split.v +++ b/test_regress/t/t_alw_split.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_alw_splitord.pl b/test_regress/t/t_alw_splitord.pl index 981bdd011..89cf5edfa 100755 --- a/test_regress/t/t_alw_splitord.pl +++ b/test_regress/t/t_alw_splitord.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_alw_splitord.v b/test_regress/t/t_alw_splitord.v index 8d1146555..f3136899f 100644 --- a/test_regress/t/t_alw_splitord.v +++ b/test_regress/t/t_alw_splitord.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_assert_basic.pl b/test_regress/t/t_assert_basic.pl index f4de78c1d..ba8e7db41 100755 --- a/test_regress/t/t_assert_basic.pl +++ b/test_regress/t/t_assert_basic.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_assert_basic.v b/test_regress/t/t_assert_basic.v index c9e1ed180..4af4a3d72 100644 --- a/test_regress/t/t_assert_basic.v +++ b/test_regress/t/t_assert_basic.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -23,7 +22,7 @@ module t (/*AUTOARG*/ // FIX cover {cyc==9} report "DefaultClock,expect=1"; // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; end - + always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; diff --git a/test_regress/t/t_assert_basic_cover.pl b/test_regress/t/t_assert_basic_cover.pl index 93405bf45..2dbe543f2 100755 --- a/test_regress/t/t_assert_basic_cover.pl +++ b/test_regress/t/t_assert_basic_cover.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_assert_basic_fail.pl b/test_regress/t/t_assert_basic_fail.pl index a0333a62d..ba4ea02e1 100755 --- a/test_regress/t/t_assert_basic_fail.pl +++ b/test_regress/t/t_assert_basic_fail.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_assert_basic_off.pl b/test_regress/t/t_assert_basic_off.pl index 52ac6bafe..d760990c5 100755 --- a/test_regress/t/t_assert_basic_off.pl +++ b/test_regress/t/t_assert_basic_off.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_assert_synth.pl b/test_regress/t/t_assert_synth.pl index f4de78c1d..ba8e7db41 100755 --- a/test_regress/t/t_assert_synth.pl +++ b/test_regress/t/t_assert_synth.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_assert_synth.v b/test_regress/t/t_assert_synth.v index e1bea1920..b50f34902 100644 --- a/test_regress/t/t_assert_synth.v +++ b/test_regress/t/t_assert_synth.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_assert_synth_full.pl b/test_regress/t/t_assert_synth_full.pl index c5cdc3380..109514d28 100755 --- a/test_regress/t/t_assert_synth_full.pl +++ b/test_regress/t/t_assert_synth_full.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_assert_synth_off.pl b/test_regress/t/t_assert_synth_off.pl index f30c208cd..77748eb79 100755 --- a/test_regress/t/t_assert_synth_off.pl +++ b/test_regress/t/t_assert_synth_off.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_assert_synth_parallel.pl b/test_regress/t/t_assert_synth_parallel.pl index ac83d515b..a1347a6bc 100755 --- a/test_regress/t/t_assert_synth_parallel.pl +++ b/test_regress/t/t_assert_synth_parallel.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_bitsel_loop.pl b/test_regress/t/t_bitsel_loop.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_bitsel_loop.pl +++ b/test_regress/t/t_bitsel_loop.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_bitsel_loop.v b/test_regress/t/t_bitsel_loop.v index ff5573025..42dc3605c 100644 --- a/test_regress/t/t_bitsel_loop.v +++ b/test_regress/t/t_bitsel_loop.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -27,7 +26,7 @@ module t (/*AUTOARG*/ end qq[27:16] = 12'hfed; end - + always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; diff --git a/test_regress/t/t_blocking.pl b/test_regress/t/t_blocking.pl index c4aacfed8..2b6dd79c0 100755 --- a/test_regress/t/t_blocking.pl +++ b/test_regress/t/t_blocking.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_blocking.v b/test_regress/t/t_blocking.v index eeaee0b80..f2df6a672 100644 --- a/test_regress/t/t_blocking.v +++ b/test_regress/t/t_blocking.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -92,5 +91,5 @@ module t (/*AUTOARG*/ if (bits !== 5'b10110) $stop; end end - + endmodule diff --git a/test_regress/t/t_case_66bits.v b/test_regress/t/t_case_66bits.v index a27eb813f..e138e316d 100644 --- a/test_regress/t/t_case_66bits.v +++ b/test_regress/t/t_case_66bits.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_case_auto1.pl b/test_regress/t/t_case_auto1.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_case_auto1.pl +++ b/test_regress/t/t_case_auto1.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_auto1.v b/test_regress/t/t_case_auto1.v index 218982264..32ea1d424 100644 --- a/test_regress/t/t_case_auto1.v +++ b/test_regress/t/t_case_auto1.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_case_deep.pl b/test_regress/t/t_case_deep.pl index c28ca5f05..af7c05a7b 100755 --- a/test_regress/t/t_case_deep.pl +++ b/test_regress/t/t_case_deep.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_deep.v b/test_regress/t/t_case_deep.v index 8d1e25c53..3e4f9d5af 100644 --- a/test_regress/t/t_case_deep.v +++ b/test_regress/t/t_case_deep.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -75,7 +74,7 @@ module Test (/*AUTOARG*/ ); input clk; - input [33:0] in; + input [33:0] in; output next; output [31:0] code; output [4:0] len; diff --git a/test_regress/t/t_case_default_bad.pl b/test_regress/t/t_case_default_bad.pl index 18098ccba..29bd9e18b 100755 --- a/test_regress/t/t_case_default_bad.pl +++ b/test_regress/t/t_case_default_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_default_bad.v b/test_regress/t/t_case_default_bad.v index d732cfa9f..3bf779978 100644 --- a/test_regress/t/t_case_default_bad.v +++ b/test_regress/t/t_case_default_bad.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_case_genx_bad.pl b/test_regress/t/t_case_genx_bad.pl index fbf032ef0..5a2e78f8f 100755 --- a/test_regress/t/t_case_genx_bad.pl +++ b/test_regress/t/t_case_genx_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_genx_bad.v b/test_regress/t/t_case_genx_bad.v index 749f2d06e..0b1411e82 100644 --- a/test_regress/t/t_case_genx_bad.v +++ b/test_regress/t/t_case_genx_bad.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_case_huge.pl b/test_regress/t/t_case_huge.pl index 27a32c742..5d46c9fa5 100755 --- a/test_regress/t/t_case_huge.pl +++ b/test_regress/t/t_case_huge.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_huge.v b/test_regress/t/t_case_huge.v index 3e305b3f4..2ddc88e6d 100644 --- a/test_regress/t/t_case_huge.v +++ b/test_regress/t/t_case_huge.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -129,14 +128,14 @@ module t (/*AUTOARG*/ .outc (outc7), // Templated // Inputs .index (index7[7:0])); // Templated - + t_case_huge_sub4 q (/*AUTOINST*/ // Outputs .outq (outq[9:0]), // Inputs .index (index[7:0])); - - + + integer cyc; initial cyc=1; initial index = 10'h0; diff --git a/test_regress/t/t_case_huge_sub.v b/test_regress/t/t_case_huge_sub.v index 819da03fc..6d6d48e79 100644 --- a/test_regress/t/t_case_huge_sub.v +++ b/test_regress/t/t_case_huge_sub.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_case_huge_sub (/*AUTOARG*/ // Outputs - outa, outb, outc, + outa, outb, outc, // Inputs index ); diff --git a/test_regress/t/t_case_huge_sub2.v b/test_regress/t/t_case_huge_sub2.v index f743eee94..45498013f 100644 --- a/test_regress/t/t_case_huge_sub2.v +++ b/test_regress/t/t_case_huge_sub2.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_case_huge_sub2 (/*AUTOARG*/ // Outputs - outa, + outa, // Inputs index ); @@ -30,7 +29,7 @@ module t_case_huge_sub2 (/*AUTOARG*/ 8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable `else 8'h00: begin outa = 10'h0; end -`endif +`endif 8'h01: begin outa = 10'h318; end 8'h02: begin outa = 10'h29f; end 8'h03: begin outa = 10'h392; end diff --git a/test_regress/t/t_case_huge_sub3.v b/test_regress/t/t_case_huge_sub3.v index 9455cada1..3afb2c86d 100644 --- a/test_regress/t/t_case_huge_sub3.v +++ b/test_regress/t/t_case_huge_sub3.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_case_huge_sub4.v b/test_regress/t/t_case_huge_sub4.v index e1e4d9909..4f36da8a9 100644 --- a/test_regress/t/t_case_huge_sub4.v +++ b/test_regress/t/t_case_huge_sub4.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_case_itemwidth.pl b/test_regress/t/t_case_itemwidth.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_case_itemwidth.pl +++ b/test_regress/t/t_case_itemwidth.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_itemwidth.v b/test_regress/t/t_case_itemwidth.v index d7e0d004e..4828f2386 100644 --- a/test_regress/t/t_case_itemwidth.v +++ b/test_regress/t/t_case_itemwidth.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_case_nest.pl b/test_regress/t/t_case_nest.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_case_nest.pl +++ b/test_regress/t/t_case_nest.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_nest.v b/test_regress/t/t_case_nest.v index 566016889..a0e910ed2 100644 --- a/test_regress/t/t_case_nest.v +++ b/test_regress/t/t_case_nest.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -58,7 +57,7 @@ module sub (/*AUTOARG*/ input [23:0] in; output reg [0:0] out1; - + parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101; always @* begin @@ -107,5 +106,5 @@ module sub (/*AUTOARG*/ endcase endcase end - + endmodule diff --git a/test_regress/t/t_case_wild.pl b/test_regress/t/t_case_wild.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_case_wild.pl +++ b/test_regress/t/t_case_wild.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_wild.v b/test_regress/t/t_case_wild.v index 1dd4eaebd..5264c38eb 100644 --- a/test_regress/t/t_case_wild.v +++ b/test_regress/t/t_case_wild.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_case_write1.pl b/test_regress/t/t_case_write1.pl index 2d8e3469d..474b9b504 100755 --- a/test_regress/t/t_case_write1.pl +++ b/test_regress/t/t_case_write1.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_write1.v b/test_regress/t/t_case_write1.v index 919609480..60375f247 100644 --- a/test_regress/t/t_case_write1.v +++ b/test_regress/t/t_case_write1.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_case_write1_tasks.v b/test_regress/t/t_case_write1_tasks.v index d3b208989..19df87e11 100644 --- a/test_regress/t/t_case_write1_tasks.v +++ b/test_regress/t/t_case_write1_tasks.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -149,7 +148,8 @@ module t_case_write1_tasks (); default:foobar = {foobar, " 128"}; endcase end - endtask + + endtask task ozonerb; input [5:0] rb; @@ -164,7 +164,7 @@ module t_case_write1_tasks (); default: ozonerab({1'b1, rb}, foobar); endcase end - endtask + endtask task ozonef3f4_iext; input [1:0] foo; @@ -211,7 +211,7 @@ module t_case_write1_tasks (); end endcase end - endtask + endtask task skyway; input [ 3:0] hex; @@ -237,7 +237,7 @@ module t_case_write1_tasks (); 4'hf : foobar = {foobar, " 149"}; endcase end - endtask + endtask task ozonesr; input [ 15:0] foo; @@ -321,7 +321,7 @@ module t_case_write1_tasks (); 3'b110 : foobar = {foobar, " 185"}; endcase end - endtask + endtask task ozonef1; input [ 31:0] foo; @@ -419,7 +419,7 @@ module t_case_write1_tasks (); 2'b10 : foobar = {foobar, " 232"}; 2'b11 : foobar = {foobar, " 233"}; endcase - endcase + endcase end endtask @@ -1552,7 +1552,7 @@ module t_case_write1_tasks (); 7'h7e, 7'h7f: foobar = {foobar," 676"}; - endcase + endcase end endtask @@ -1672,7 +1672,7 @@ module t_case_write1_tasks (); endcase endcase end - endtask + endtask task ozonef2e; input [ 31:0] foo; @@ -1872,7 +1872,7 @@ module t_case_write1_tasks (); foobar = {foobar," 794"}; endcase end - endtask + endtask task ozonef3e; input [ 31:0] foo; @@ -1992,7 +1992,7 @@ module t_case_write1_tasks (); foobar = {foobar," 822"}; endcase end - endtask + endtask task ozonef3e_te; input [ 2:0] te; inout [STRLEN*8: 1] foobar; @@ -2005,7 +2005,7 @@ module t_case_write1_tasks (); default: foobar = {foobar, " 826"}; endcase end - endtask + endtask task ozonearm; input [ 2:0] ate; inout [STRLEN*8: 1] foobar; @@ -2121,7 +2121,7 @@ module t_case_write1_tasks (); foobar = {foobar, " 867"}; nacho = 1'b1; end - endcase + endcase if (~nacho) begin case (foo[24:21]) @@ -2257,7 +2257,7 @@ module t_case_write1_tasks (); 4'hf: foobar = {foobar, " 905"}; endcase end - endtask + endtask task ozonef1e_hl; input [ 2:0] e; input l; @@ -2453,7 +2453,7 @@ module t_case_write1_tasks (); end endtask task ozoneacc; - input foo; + input foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin @@ -2464,7 +2464,7 @@ module t_case_write1_tasks (); end endtask task ozonehl; - input foo; + input foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin @@ -2477,7 +2477,7 @@ module t_case_write1_tasks (); task dude; inout [STRLEN*8: 1] foobar; reg [ 7:0] temp; - integer i; + integer i; reg nacho; // verilator no_inline_task begin : justify_block @@ -2492,17 +2492,17 @@ module t_case_write1_tasks (); foobar = foobar<<8; foobar[8:1] = 32; end - end + end end endtask task big_case; `ifdef verilator - input [ 63:0] fd; + input [ 63:0] fd; `else - input [ 31:0] fd; + input [ 31:0] fd; `endif - input [ 31:0] foo; + input [ 31:0] foo; reg [STRLEN*8: 1] foobar; // verilator no_inline_task begin @@ -3024,7 +3024,7 @@ module t_case_write1_tasks (); $fwrite (fd, " 1176:%s", foobar); end default: foobar = {foobar, " 1177"}; - endcase + endcase 17'b00_10??_?_????_?0_110? : begin ozonef1e(foo, foobar); @@ -3788,8 +3788,8 @@ module t_case_write1_tasks (); else $fwrite(fd, " 1409:%s", foo[22:16]); default: $fwrite(fd, " 1410"); - endcase - end + endcase + end endtask //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) diff --git a/test_regress/t/t_case_write2.pl b/test_regress/t/t_case_write2.pl index 2d8e3469d..474b9b504 100755 --- a/test_regress/t/t_case_write2.pl +++ b/test_regress/t/t_case_write2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_write2.v b/test_regress/t/t_case_write2.v index 036cc608b..05f1adee6 100644 --- a/test_regress/t/t_case_write2.v +++ b/test_regress/t/t_case_write2.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_case_write2_tasks.v b/test_regress/t/t_case_write2_tasks.v index 475818418..e0e2bf537 100644 --- a/test_regress/t/t_case_write2_tasks.v +++ b/test_regress/t/t_case_write2_tasks.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -155,7 +154,7 @@ module t_case_write2_tasks (); default:$fwrite (fd, " 128"); endcase end - endtask + endtask task ozonerb; input [5:0] rb; @@ -170,7 +169,7 @@ module t_case_write2_tasks (); default: ozonerab({1'b1, rb}, fd); endcase end - endtask + endtask task ozonef3f4_iext; input [1:0] foo; @@ -217,7 +216,7 @@ module t_case_write2_tasks (); end endcase end - endtask + endtask task skyway; input [ 3:0] hex; @@ -243,7 +242,7 @@ module t_case_write2_tasks (); 4'hf : $fwrite (fd, " 149"); endcase end - endtask + endtask task ozonesr; input [ 15:0] foo; @@ -327,7 +326,7 @@ module t_case_write2_tasks (); 3'b110 : $fwrite (fd, " 185"); endcase end - endtask + endtask task ozonef1; input [ 31:0] foo; @@ -425,7 +424,7 @@ module t_case_write2_tasks (); 2'b10 : $fwrite (fd, " 232"); 2'b11 : $fwrite (fd, " 233"); endcase - endcase + endcase end endtask @@ -1558,7 +1557,7 @@ module t_case_write2_tasks (); 7'h7e, 7'h7f: $fwrite (fd," 676"); - endcase + endcase end endtask @@ -1678,7 +1677,7 @@ module t_case_write2_tasks (); endcase endcase end - endtask + endtask task ozonef2e; input [ 31:0] foo; @@ -1878,7 +1877,7 @@ module t_case_write2_tasks (); $fwrite (fd," 794"); endcase end - endtask + endtask task ozonef3e; input [ 31:0] foo; @@ -1998,7 +1997,7 @@ module t_case_write2_tasks (); $fwrite (fd," 822"); endcase end - endtask + endtask task ozonef3e_te; input [ 2:0] te; input [`FD_BITS] fd; @@ -2011,7 +2010,7 @@ module t_case_write2_tasks (); default: $fwrite (fd, " 826"); endcase end - endtask + endtask task ozonearm; input [ 2:0] ate; input [`FD_BITS] fd; @@ -2127,7 +2126,7 @@ module t_case_write2_tasks (); $fwrite (fd, " 867"); nacho = 1'b1; end - endcase + endcase if (~nacho) begin case (foo[24:21]) @@ -2263,7 +2262,7 @@ module t_case_write2_tasks (); 4'hf: $fwrite (fd, " 905"); endcase end - endtask + endtask task ozonef1e_hl; input [ 2:0] e; input l; @@ -2459,7 +2458,7 @@ module t_case_write2_tasks (); end endtask task ozoneacc; - input foo; + input foo; input [`FD_BITS] fd; // verilator no_inline_task begin @@ -2470,7 +2469,7 @@ module t_case_write2_tasks (); end endtask task ozonehl; - input foo; + input foo; input [`FD_BITS] fd; // verilator no_inline_task begin @@ -2487,8 +2486,8 @@ module t_case_write2_tasks (); endtask task big_case; - input [ `FD_BITS] fd; - input [ 31:0] foo; + input [ `FD_BITS] fd; + input [ 31:0] foo; // verilator no_inline_task begin $fwrite(fd," 1009"); @@ -3009,7 +3008,7 @@ module t_case_write2_tasks (); $fwrite (fd, " 1176"); end default: $fwrite (fd, " 1177"); - endcase + endcase 17'b00_10??_?_????_?0_110? : begin ozonef1e(foo, fd); @@ -3768,8 +3767,8 @@ module t_case_write2_tasks (); else $fwrite(fd, " 1409:%x", foo[22:16]); default: $fwrite(fd, " 1410"); - endcase - end + endcase + end endtask //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) diff --git a/test_regress/t/t_case_x_bad.pl b/test_regress/t/t_case_x_bad.pl index 916a147c7..19dcf964b 100755 --- a/test_regress/t/t_case_x_bad.pl +++ b/test_regress/t/t_case_x_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_case_x_bad.v b/test_regress/t/t_case_x_bad.v index 4e5d2e1c3..4e7a5866b 100644 --- a/test_regress/t/t_case_x_bad.v +++ b/test_regress/t/t_case_x_bad.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_clk_condflop.pl b/test_regress/t/t_clk_condflop.pl index a9bd24155..7b54e1f21 100755 --- a/test_regress/t/t_clk_condflop.pl +++ b/test_regress/t/t_clk_condflop.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_clk_condflop.v b/test_regress/t/t_clk_condflop.v index 369b60d3d..5554ecb07 100644 --- a/test_regress/t/t_clk_condflop.v +++ b/test_regress/t/t_clk_condflop.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_clk_dpulse.pl b/test_regress/t/t_clk_dpulse.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_clk_dpulse.pl +++ b/test_regress/t/t_clk_dpulse.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_clk_dpulse.v b/test_regress/t/t_clk_dpulse.v index 79ee8836a..1fa080c76 100644 --- a/test_regress/t/t_clk_dpulse.v +++ b/test_regress/t/t_clk_dpulse.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_clk_dsp.pl b/test_regress/t/t_clk_dsp.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_clk_dsp.pl +++ b/test_regress/t/t_clk_dsp.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_clk_dsp.v b/test_regress/t/t_clk_dsp.v index a4e593d9f..991b9754e 100644 --- a/test_regress/t/t_clk_dsp.v +++ b/test_regress/t/t_clk_dsp.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -78,21 +77,21 @@ endmodule module t_dspchip (/*AUTOARG*/ // Outputs - out, + out, // Inputs dsp_ph1, dsp_ph2, dsp_reset, padd ); input dsp_ph1, dsp_ph2, dsp_reset; input [7:0] padd; output [7:0] out; - + wire dsp_ph1, dsp_ph2; wire [7:0] out; wire pla_ph1, pla_ph2; wire out1_r; wire [7:0] out2_r, padd; wire clk_en; - + t_dspcore t_dspcore (/*AUTOINST*/ // Outputs .out1_r (out1_r), @@ -111,33 +110,33 @@ module t_dspchip (/*AUTOARG*/ .pla_ph2 (pla_ph2), .dsp_reset (dsp_reset), .padd (padd[7:0])); - + assign out = out1_r ? 8'h00 : out2_r; assign clk_en = 1'b1; - + endmodule module t_dspcore (/*AUTOARG*/ // Outputs - out1_r, pla_ph1, pla_ph2, + out1_r, pla_ph1, pla_ph2, // Inputs dsp_ph1, dsp_ph2, dsp_reset, clk_en ); input dsp_ph1, dsp_ph2, dsp_reset; input clk_en; output out1_r, pla_ph1, pla_ph2; - + wire dsp_ph1, dsp_ph2, dsp_reset; wire pla_ph1, pla_ph2; reg out1_r; - + always @(posedge dsp_ph1 or posedge dsp_reset) begin if (dsp_reset) out1_r <= 1'h0; else out1_r <= ~out1_r; end - + assign pla_ph1 = dsp_ph1; assign pla_ph2 = dsp_ph2 & clk_en; @@ -145,32 +144,32 @@ endmodule module t_dsppla (/*AUTOARG*/ // Outputs - out2_r, + out2_r, // Inputs pla_ph1, pla_ph2, dsp_reset, padd ); input pla_ph1, pla_ph2, dsp_reset; input [7:0] padd; output [7:0] out2_r; - + wire pla_ph1, pla_ph2, dsp_reset; wire [7:0] padd; reg [7:0] out2_r; - + reg [7:0] latched_r; - + always @(posedge pla_ph1 or posedge dsp_reset) begin if (dsp_reset) latched_r <= 8'h00; else latched_r <= padd; end - + always @(posedge pla_ph2 or posedge dsp_reset) begin if (dsp_reset) out2_r <= 8'h00; else out2_r <= latched_r; end - + endmodule diff --git a/test_regress/t/t_clk_gen.pl b/test_regress/t/t_clk_gen.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_clk_gen.pl +++ b/test_regress/t/t_clk_gen.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_clk_gen.v b/test_regress/t/t_clk_gen.v index 05aebe44e..8042d287f 100644 --- a/test_regress/t/t_clk_gen.v +++ b/test_regress/t/t_clk_gen.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_clk_latch.pl b/test_regress/t/t_clk_latch.pl index a9bd24155..7b54e1f21 100755 --- a/test_regress/t/t_clk_latch.pl +++ b/test_regress/t/t_clk_latch.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_clk_latch.v b/test_regress/t/t_clk_latch.v index b7bbd070d..18ec5fe72 100644 --- a/test_regress/t/t_clk_latch.v +++ b/test_regress/t/t_clk_latch.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -13,7 +12,7 @@ module t (/*AUTOARG*/ `define posstyle posedge `define negstyle negedge `else - `define posstyle + `define posstyle `define negstyle `endif diff --git a/test_regress/t/t_clk_latch_edgestyle.pl b/test_regress/t/t_clk_latch_edgestyle.pl index 766cc39d3..1a400a8b2 100755 --- a/test_regress/t/t_clk_latch_edgestyle.pl +++ b/test_regress/t/t_clk_latch_edgestyle.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_clk_powerdn.pl b/test_regress/t/t_clk_powerdn.pl index a9bd24155..7b54e1f21 100755 --- a/test_regress/t/t_clk_powerdn.pl +++ b/test_regress/t/t_clk_powerdn.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_clk_powerdn.v b/test_regress/t/t_clk_powerdn.v index f15992ef0..e6bb09fc1 100644 --- a/test_regress/t/t_clk_powerdn.v +++ b/test_regress/t/t_clk_powerdn.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_delay.pl b/test_regress/t/t_delay.pl index 03c734192..60d2a2144 100755 --- a/test_regress/t/t_delay.pl +++ b/test_regress/t/t_delay.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_delay.v b/test_regress/t/t_delay.v index 9975014e7..446dfe34b 100644 --- a/test_regress/t/t_delay.v +++ b/test_regress/t/t_delay.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -9,7 +8,7 @@ module t (/*AUTOARG*/ clk ); parameter PAR = 3; - + input clk; integer cyc=1; diff --git a/test_regress/t/t_delay_stmtdly_bad.pl b/test_regress/t/t_delay_stmtdly_bad.pl index b11fce807..055b5be28 100755 --- a/test_regress/t/t_delay_stmtdly_bad.pl +++ b/test_regress/t/t_delay_stmtdly_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_display.pl b/test_regress/t/t_display.pl index 2c75873ae..024f5b0ee 100755 --- a/test_regress/t/t_display.pl +++ b/test_regress/t/t_display.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v index 44e2520c6..490ecbc35 100644 --- a/test_regress/t/t_display.v +++ b/test_regress/t/t_display.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_display_bad.pl b/test_regress/t/t_display_bad.pl index 59dda774c..f1f8bad74 100755 --- a/test_regress/t/t_display_bad.pl +++ b/test_regress/t/t_display_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_display_bad.v b/test_regress/t/t_display_bad.v index 130a9c0e4..fda28df89 100644 --- a/test_regress/t/t_display_bad.v +++ b/test_regress/t/t_display_bad.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_display_noopt.pl b/test_regress/t/t_display_noopt.pl index 90bd37f2c..99e6afaed 100755 --- a/test_regress/t/t_display_noopt.pl +++ b/test_regress/t/t_display_noopt.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_display_signed.pl b/test_regress/t/t_display_signed.pl index 825e3e655..d33edfc06 100755 --- a/test_regress/t/t_display_signed.pl +++ b/test_regress/t/t_display_signed.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_display_signed.v b/test_regress/t/t_display_signed.v index 0c09ed19e..c7b29c5f9 100644 --- a/test_regress/t/t_display_signed.v +++ b/test_regress/t/t_display_signed.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_display_signed_noopt.pl b/test_regress/t/t_display_signed_noopt.pl index 2a5032e9e..db3a58e18 100755 --- a/test_regress/t/t_display_signed_noopt.pl +++ b/test_regress/t/t_display_signed_noopt.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_dist_manifest.pl b/test_regress/t/t_dist_manifest.pl index ec8af52dc..29f1a58c7 100755 --- a/test_regress/t/t_dist_manifest.pl +++ b/test_regress/t/t_dist_manifest.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_dos.pl b/test_regress/t/t_dos.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_dos.pl +++ b/test_regress/t/t_dos.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_dos.v b/test_regress/t/t_dos.v index 24709f8b4..1b239bf33 100755 --- a/test_regress/t/t_dos.v +++ b/test_regress/t/t_dos.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_emit_constw.pl b/test_regress/t/t_emit_constw.pl index a7e6a1f20..42671133c 100755 --- a/test_regress/t/t_emit_constw.pl +++ b/test_regress/t/t_emit_constw.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_emit_constw.v b/test_regress/t/t_emit_constw.v index 47398828c..9c85821fb 100644 --- a/test_regress/t/t_emit_constw.v +++ b/test_regress/t/t_emit_constw.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module module t (/*AUTOARG*/ diff --git a/test_regress/t/t_extend.pl b/test_regress/t/t_extend.pl index 879365342..31536dbe5 100755 --- a/test_regress/t/t_extend.pl +++ b/test_regress/t/t_extend.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_extend.v b/test_regress/t/t_extend.v index 2dd9368dd..738ba779a 100644 --- a/test_regress/t/t_extend.v +++ b/test_regress/t/t_extend.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -37,9 +36,9 @@ module t (/*AUTOARG*/ c_worked <= $c("my_function()"); c_wider <= $c9("0x10"); `else - c_worked <= 1'b1; + c_worked <= 1'b1; c_wider <= 9'h10; -`endif +`endif end if (cyc == 8'd3) begin if (c_worked !== 1'b1) $stop; @@ -67,12 +66,12 @@ module t (/*AUTOARG*/ #error "`systemc_imp_header didn't work" #endif `systemc_ctor - m_did_ctor = 1; + m_did_ctor = 1; `systemc_dtor printf("In systemc_dtor\n"); printf("*-* All Finished *-*\n"); `verilog -`endif +`endif endmodule diff --git a/test_regress/t/t_extend_class.pl b/test_regress/t/t_extend_class.pl index bb71c3675..0a0421cc5 100755 --- a/test_regress/t/t_extend_class.pl +++ b/test_regress/t/t_extend_class.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_extend_class.v b/test_regress/t/t_extend_class.v index b0b253974..fa3e3bcb4 100644 --- a/test_regress/t/t_extend_class.v +++ b/test_regress/t/t_extend_class.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_extend_class_c.h b/test_regress/t/t_extend_class_c.h index 7323b9fb6..52dc93c4e 100644 --- a/test_regress/t/t_extend_class_c.h +++ b/test_regress/t/t_extend_class_c.h @@ -1,4 +1,4 @@ -// $Id$ -*- C++ -*- +// -*- C++ -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_flag_f.pl b/test_regress/t/t_flag_f.pl index 059006dd0..e146a865c 100755 --- a/test_regress/t/t_flag_f.pl +++ b/test_regress/t/t_flag_f.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_flag_f.v b/test_regress/t/t_flag_f.v index 04eaec8af..09e3f50d1 100644 --- a/test_regress/t/t_flag_f.v +++ b/test_regress/t/t_flag_f.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module module t; diff --git a/test_regress/t/t_flag_language.v b/test_regress/t/t_flag_language.v index 124a7f985..4c3c8b6ef 100644 --- a/test_regress/t/t_flag_language.v +++ b/test_regress/t/t_flag_language.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_flag_lib.v b/test_regress/t/t_flag_lib.v index 0acb6d16e..012bf7104 100644 --- a/test_regress/t/t_flag_lib.v +++ b/test_regress/t/t_flag_lib.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_flag_libinc.v b/test_regress/t/t_flag_libinc.v index bf69899ec..26769e48b 100644 --- a/test_regress/t/t_flag_libinc.v +++ b/test_regress/t/t_flag_libinc.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_flag_nomod_bad.pl b/test_regress/t/t_flag_nomod_bad.pl index 2b7049696..b30584584 100755 --- a/test_regress/t/t_flag_nomod_bad.pl +++ b/test_regress/t/t_flag_nomod_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_flag_nomod_bad.v b/test_regress/t/t_flag_nomod_bad.v index 579cf70b0..99a0ead12 100644 --- a/test_regress/t/t_flag_nomod_bad.v +++ b/test_regress/t/t_flag_nomod_bad.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_flag_skipidentical.pl b/test_regress/t/t_flag_skipidentical.pl index 9a15c393e..88f406a06 100755 --- a/test_regress/t/t_flag_skipidentical.pl +++ b/test_regress/t/t_flag_skipidentical.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_flag_skipidentical.v b/test_regress/t/t_flag_skipidentical.v index 6c9e2d06b..7e30bb838 100644 --- a/test_regress/t/t_flag_skipidentical.v +++ b/test_regress/t/t_flag_skipidentical.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_flag_topmodule.pl b/test_regress/t/t_flag_topmodule.pl index d82447192..45cfd9998 100755 --- a/test_regress/t/t_flag_topmodule.pl +++ b/test_regress/t/t_flag_topmodule.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_flag_topmodule.v b/test_regress/t/t_flag_topmodule.v index 417cfd9a6..d17cfee20 100644 --- a/test_regress/t/t_flag_topmodule.v +++ b/test_regress/t/t_flag_topmodule.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_flag_topmodule_bad.pl b/test_regress/t/t_flag_topmodule_bad.pl index 1a44820aa..227aa9fa3 100755 --- a/test_regress/t/t_flag_topmodule_bad.pl +++ b/test_regress/t/t_flag_topmodule_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_flag_topmodule_bad2.pl b/test_regress/t/t_flag_topmodule_bad2.pl index 841e8b0ec..e456f1e6b 100755 --- a/test_regress/t/t_flag_topmodule_bad2.pl +++ b/test_regress/t/t_flag_topmodule_bad2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_flag_werror.v b/test_regress/t/t_flag_werror.v index fc5b7fc03..11acd8683 100644 --- a/test_regress/t/t_flag_werror.v +++ b/test_regress/t/t_flag_werror.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_flag_werror_bad1.pl b/test_regress/t/t_flag_werror_bad1.pl index 2aeae5d19..074428df5 100755 --- a/test_regress/t/t_flag_werror_bad1.pl +++ b/test_regress/t/t_flag_werror_bad1.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_flag_werror_bad2.pl b/test_regress/t/t_flag_werror_bad2.pl index 9312ec010..4d5fb5899 100755 --- a/test_regress/t/t_flag_werror_bad2.pl +++ b/test_regress/t/t_flag_werror_bad2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_for_count.pl b/test_regress/t/t_for_count.pl index eff491d7a..2b6dd79c0 100755 --- a/test_regress/t/t_for_count.pl +++ b/test_regress/t/t_for_count.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_for_count.v b/test_regress/t/t_for_count.v index 34bd66455..99ac6d48c 100644 --- a/test_regress/t/t_for_count.v +++ b/test_regress/t/t_for_count.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_for_funcbound.pl b/test_regress/t/t_for_funcbound.pl index 6ddb50037..cb29abdc5 100755 --- a/test_regress/t/t_for_funcbound.pl +++ b/test_regress/t/t_for_funcbound.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_for_funcbound.v b/test_regress/t/t_for_funcbound.v index 354b017bc..5a098d433 100644 --- a/test_regress/t/t_for_funcbound.v +++ b/test_regress/t/t_for_funcbound.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func.pl b/test_regress/t/t_func.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_func.pl +++ b/test_regress/t/t_func.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func.v b/test_regress/t/t_func.v index 8066959c6..fd175353e 100644 --- a/test_regress/t/t_func.v +++ b/test_regress/t/t_func.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -32,7 +31,7 @@ module t; if (nil_func(32'h12,32'h12) != 32'h24) $stop; nil_task(32'h012,32'h112,global); if (global !== 32'h124) $stop; - + vec[0] = 32'h333; vec[1] = 32'habc; incr(vec[1],vec[0],vec[1]); diff --git a/test_regress/t/t_func_bad.pl b/test_regress/t/t_func_bad.pl index 5077610ac..6df5b648f 100755 --- a/test_regress/t/t_func_bad.pl +++ b/test_regress/t/t_func_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_bad.v b/test_regress/t/t_func_bad.v index b1d8cd206..22391e509 100644 --- a/test_regress/t/t_func_bad.v +++ b/test_regress/t/t_func_bad.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_bad2.pl b/test_regress/t/t_func_bad2.pl index 0bb5677b0..e77bf9302 100755 --- a/test_regress/t/t_func_bad2.pl +++ b/test_regress/t/t_func_bad2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_bad2.v b/test_regress/t/t_func_bad2.v index 1cf093a73..b90fa084c 100644 --- a/test_regress/t/t_func_bad2.v +++ b/test_regress/t/t_func_bad2.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_bad_width.pl b/test_regress/t/t_func_bad_width.pl index cefa7f5f0..a0802aac3 100755 --- a/test_regress/t/t_func_bad_width.pl +++ b/test_regress/t/t_func_bad_width.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_bad_width.v b/test_regress/t/t_func_bad_width.v index f9fa5e08c..163d9ff5f 100644 --- a/test_regress/t/t_func_bad_width.v +++ b/test_regress/t/t_func_bad_width.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_check.pl b/test_regress/t/t_func_check.pl index 638d58458..76e1d0081 100755 --- a/test_regress/t/t_func_check.pl +++ b/test_regress/t/t_func_check.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_check.v b/test_regress/t/t_func_check.v index ad1459459..943e79820 100644 --- a/test_regress/t/t_func_check.v +++ b/test_regress/t/t_func_check.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // verilator lint_off WIDTH @@ -42,7 +41,7 @@ module chk (input clk, input rst_l, input expr); $write("%%Error: %0s\n", msg); $stop; end - endtask + endtask always @(posedge clk) begin if (rst_l) begin @@ -72,4 +71,4 @@ module chk (input clk, input rst_l, input expr); end end -endmodule +endmodule diff --git a/test_regress/t/t_func_crc.pl b/test_regress/t/t_func_crc.pl index c28ca5f05..af7c05a7b 100755 --- a/test_regress/t/t_func_crc.pl +++ b/test_regress/t/t_func_crc.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_crc.v b/test_regress/t/t_func_crc.v index ccacc639a..cd9f98c61 100644 --- a/test_regress/t/t_func_crc.v +++ b/test_regress/t/t_func_crc.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_dotted.v b/test_regress/t/t_func_dotted.v index 789b5335e..db26d460e 100644 --- a/test_regress/t/t_func_dotted.v +++ b/test_regress/t/t_func_dotted.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -8,7 +7,7 @@ module t (/*AUTOARG*/ // Inputs clk ); - + // verilator lint_off MULTIDRIVEN ma ma0 (); diff --git a/test_regress/t/t_func_dotted_inl0.pl b/test_regress/t/t_func_dotted_inl0.pl index bfbd3fc66..27dc19c61 100755 --- a/test_regress/t/t_func_dotted_inl0.pl +++ b/test_regress/t/t_func_dotted_inl0.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_dotted_inl1.pl b/test_regress/t/t_func_dotted_inl1.pl index 52fabc6b5..665255572 100755 --- a/test_regress/t/t_func_dotted_inl1.pl +++ b/test_regress/t/t_func_dotted_inl1.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_dotted_inl2.pl b/test_regress/t/t_func_dotted_inl2.pl index 4f42af1bf..43e888dea 100755 --- a/test_regress/t/t_func_dotted_inl2.pl +++ b/test_regress/t/t_func_dotted_inl2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_endian.pl b/test_regress/t/t_func_endian.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_func_endian.pl +++ b/test_regress/t/t_func_endian.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_endian.v b/test_regress/t/t_func_endian.v index 606d480d4..5df5ca198 100644 --- a/test_regress/t/t_func_endian.v +++ b/test_regress/t/t_func_endian.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -77,7 +76,7 @@ module Test (/*AUTOARG*/ input noswap; input nibble; - input [31:0] in; + input [31:0] in; output [31:0] out; output [31:0] swapped; @@ -88,9 +87,9 @@ module Test (/*AUTOARG*/ EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3], Data[4], Data[5], Data[6], Data[7] } : { 4'h0, Data[0], Data[1], Data[2], Data[3] }); - end + end endfunction - + assign out[31:24] = (noswap ? in[31:24] : EndianSwap(nibble, in[31:24])); assign out[23:16] = (noswap ? in[23:16] @@ -99,7 +98,7 @@ module Test (/*AUTOARG*/ : EndianSwap(nibble, in[15:8])); assign out[7:0] = (noswap ? in[7:0] : EndianSwap(nibble, in[7:0])); - + reg [31:0] swapped; always @(posedge clk) begin swapped[31:24] <= EndianSwap(nibble, in[31:24]); diff --git a/test_regress/t/t_func_flip.pl b/test_regress/t/t_func_flip.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_func_flip.pl +++ b/test_regress/t/t_func_flip.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_flip.v b/test_regress/t/t_func_flip.v index 55fa39689..3628599b6 100644 --- a/test_regress/t/t_func_flip.v +++ b/test_regress/t/t_func_flip.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -23,17 +22,17 @@ module t (clk); input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector reg [`VECTOR_RANGE] flip; begin - flip = 'd0; - func_tree_left = flip; + flip = 'd0; + func_tree_left = flip; end endfunction - + reg [WIDTH-1:0] a; // value to be shifted reg [WIDTH-1:0] tree_left; always @(a) begin : barrel_shift tree_left = func_tree_left (a); end // barrel_shift - + integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin diff --git a/test_regress/t/t_func_graphcirc.pl b/test_regress/t/t_func_graphcirc.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_func_graphcirc.pl +++ b/test_regress/t/t_func_graphcirc.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_graphcirc.v b/test_regress/t/t_func_graphcirc.v index 49fa75031..562962f1b 100644 --- a/test_regress/t/t_func_graphcirc.v +++ b/test_regress/t/t_func_graphcirc.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_lib.pl b/test_regress/t/t_func_lib.pl index 6cb6deac8..1cbef398b 100755 --- a/test_regress/t/t_func_lib.pl +++ b/test_regress/t/t_func_lib.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_lib.v b/test_regress/t/t_func_lib.v index 7921f758f..6686d7352 100644 --- a/test_regress/t/t_func_lib.v +++ b/test_regress/t/t_func_lib.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_lib_sub.pl b/test_regress/t/t_func_lib_sub.pl index f1d335e09..538f2a89a 100755 --- a/test_regress/t/t_func_lib_sub.pl +++ b/test_regress/t/t_func_lib_sub.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_lib_sub.v b/test_regress/t/t_func_lib_sub.v index f2d250081..1e11802c3 100644 --- a/test_regress/t/t_func_lib_sub.v +++ b/test_regress/t/t_func_lib_sub.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -34,7 +33,7 @@ wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1); wire smxixw = vrqrih | (ryyjxy & ktsveg); wire [7:0] grvsrs, kyxrft, uxhkka; - + wire [7:0] eianuv = 8'h01 << ofnjjt; wire [7:0] jvpnxn = {8{qnpfus}} & eianuv; wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv; @@ -94,7 +93,7 @@ begin Xinit; if (X(qqibou)) udbvtl <= #`zednkw mppedc; - + Xcheck(fgzsox); end diff --git a/test_regress/t/t_func_mlog2.pl b/test_regress/t/t_func_mlog2.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_func_mlog2.pl +++ b/test_regress/t/t_func_mlog2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_mlog2.v b/test_regress/t/t_func_mlog2.v index 286c5fc99..bddb2c8e7 100644 --- a/test_regress/t/t_func_mlog2.v +++ b/test_regress/t/t_func_mlog2.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_numones.pl b/test_regress/t/t_func_numones.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_func_numones.pl +++ b/test_regress/t/t_func_numones.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_numones.v b/test_regress/t/t_func_numones.v index 5a86d5470..e47fa50dd 100644 --- a/test_regress/t/t_func_numones.v +++ b/test_regress/t/t_func_numones.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_outp.pl b/test_regress/t/t_func_outp.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_func_outp.pl +++ b/test_regress/t/t_func_outp.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_outp.v b/test_regress/t/t_func_outp.v index 47e3a721a..46051ddb1 100644 --- a/test_regress/t/t_func_outp.v +++ b/test_regress/t/t_func_outp.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -71,7 +70,7 @@ module ftest( always @ ( posedge clk ) begin z <= myadd( a, zi ); end - + function [ 7:0 ] myadd; input [7:0] ina; input [7:0] inb; @@ -83,7 +82,7 @@ module ftest( endmodule // ftest -module mytop ( +module mytop ( input [ 7:0 ] a, b, input clk, diff --git a/test_regress/t/t_func_paramed.pl b/test_regress/t/t_func_paramed.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_func_paramed.pl +++ b/test_regress/t/t_func_paramed.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_paramed.v b/test_regress/t/t_func_paramed.v index 21cdc05c6..c9ccf9b29 100644 --- a/test_regress/t/t_func_paramed.v +++ b/test_regress/t/t_func_paramed.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_plog.pl b/test_regress/t/t_func_plog.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_func_plog.pl +++ b/test_regress/t/t_func_plog.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_plog.v b/test_regress/t/t_func_plog.v index 616ad559c..0f1e883b2 100644 --- a/test_regress/t/t_func_plog.v +++ b/test_regress/t/t_func_plog.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_public.pl b/test_regress/t/t_func_public.pl index 58ca2309c..2ec9b5308 100755 --- a/test_regress/t/t_func_public.pl +++ b/test_regress/t/t_func_public.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_public.v b/test_regress/t/t_func_public.v index 00e6ddec5..bf87498e1 100644 --- a/test_regress/t/t_func_public.v +++ b/test_regress/t/t_func_public.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_public_trace.pl b/test_regress/t/t_func_public_trace.pl index c42a59b04..c38d7a5c5 100755 --- a/test_regress/t/t_func_public_trace.pl +++ b/test_regress/t/t_func_public_trace.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_rand.cpp b/test_regress/t/t_func_rand.cpp index 1a0daa8e6..0877c25d7 100644 --- a/test_regress/t/t_func_rand.cpp +++ b/test_regress/t/t_func_rand.cpp @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_rand.pl b/test_regress/t/t_func_rand.pl index c21411c10..68ea871d1 100755 --- a/test_regress/t/t_func_rand.pl +++ b/test_regress/t/t_func_rand.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_rand.v b/test_regress/t/t_func_rand.v index 580c1d063..0d525bb9b 100644 --- a/test_regress/t/t_func_rand.v +++ b/test_regress/t/t_func_rand.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_range.pl b/test_regress/t/t_func_range.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_func_range.pl +++ b/test_regress/t/t_func_range.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_range.v b/test_regress/t/t_func_range.v index 7ccb61fe9..fc29e9ec0 100644 --- a/test_regress/t/t_func_range.v +++ b/test_regress/t/t_func_range.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -12,14 +11,14 @@ module t (clk); `define INT_RANGE 31:0 `define INT_RANGE_MAX 31 `define VECTOR_RANGE 63:0 - + reg [`INT_RANGE] stashb, stasha, stashn, stashm; function [`VECTOR_RANGE] copy_range; input [`VECTOR_RANGE] y; input [`INT_RANGE] b; input [`INT_RANGE] a; - + input [`VECTOR_RANGE] x; input [`INT_RANGE] n; input [`INT_RANGE] m; @@ -36,7 +35,7 @@ module t (clk); parameter DATA_SIZE = 16; parameter NUM_OF_REGS = 32; - reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; + reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; reg [DATA_SIZE-1:0] memread_rf_reg; always @(memread_rf) begin : memread_convert memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf, diff --git a/test_regress/t/t_func_regfirst.pl b/test_regress/t/t_func_regfirst.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_func_regfirst.pl +++ b/test_regress/t/t_func_regfirst.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_regfirst.v b/test_regress/t/t_func_regfirst.v index 97761db0a..ca3e2dcb2 100644 --- a/test_regress/t/t_func_regfirst.v +++ b/test_regress/t/t_func_regfirst.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_twocall.pl b/test_regress/t/t_func_twocall.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_func_twocall.pl +++ b/test_regress/t/t_func_twocall.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_twocall.v b/test_regress/t/t_func_twocall.v index d2b8b680d..324166c72 100644 --- a/test_regress/t/t_func_twocall.v +++ b/test_regress/t/t_func_twocall.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_func_wide.pl b/test_regress/t/t_func_wide.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_func_wide.pl +++ b/test_regress/t/t_func_wide.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_func_wide.v b/test_regress/t/t_func_wide.v index 2749c8627..b7e398e18 100644 --- a/test_regress/t/t_func_wide.v +++ b/test_regress/t/t_func_wide.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -28,7 +27,7 @@ module t (clk); endmodule -module muxtop ( +module muxtop ( input [ 43:0 ] i, output reg [ 31:0 ] o ); diff --git a/test_regress/t/t_gate_basic.pl b/test_regress/t/t_gate_basic.pl index eff491d7a..2b6dd79c0 100755 --- a/test_regress/t/t_gate_basic.pl +++ b/test_regress/t/t_gate_basic.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gate_basic.v b/test_regress/t/t_gate_basic.v index e5a721002..5417c4370 100644 --- a/test_regress/t/t_gate_basic.v +++ b/test_regress/t/t_gate_basic.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -14,7 +13,7 @@ module t (/*AUTOARG*/ reg [31:0] a; reg [31:0] b; - + wire [2:0] bf; buf BF0 (bf[0], a[0]), BF1 (bf[1], a[1]), BF2 (bf[2], a[2]); diff --git a/test_regress/t/t_gate_elim.pl b/test_regress/t/t_gate_elim.pl index c4aacfed8..2b6dd79c0 100755 --- a/test_regress/t/t_gate_elim.pl +++ b/test_regress/t/t_gate_elim.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gate_elim.v b/test_regress/t/t_gate_elim.v index 7d0519b0c..fbb327380 100644 --- a/test_regress/t/t_gate_elim.v +++ b/test_regress/t/t_gate_elim.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -13,7 +12,7 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; reg b; - + wire vconst1 = 1'b0; wire vconst2 = !(vconst1); wire vconst3 = !vconst2; @@ -76,7 +75,7 @@ module ta ( q = vconst | b; end endmodule - + module tb ( input vconst, input clk, @@ -106,7 +105,7 @@ module td ( q = vconst; end endmodule - + module te ( input clk, input vconst, diff --git a/test_regress/t/t_gen_assign.pl b/test_regress/t/t_gen_assign.pl index a9e251789..9690e9fa6 100755 --- a/test_regress/t/t_gen_assign.pl +++ b/test_regress/t/t_gen_assign.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gen_assign.v b/test_regress/t/t_gen_assign.v index ad011d8b2..838d880d8 100644 --- a/test_regress/t/t_gen_assign.v +++ b/test_regress/t/t_gen_assign.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty. @@ -50,7 +49,7 @@ endmodule module assigns(Input, Output); input [8:0] Input; output [8:0] Output; - + genvar i; generate for (i = 0; i < 8; i = i + 1) begin : ap diff --git a/test_regress/t/t_gen_for.pl b/test_regress/t/t_gen_for.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_gen_for.pl +++ b/test_regress/t/t_gen_for.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gen_for.v b/test_regress/t/t_gen_for.v index 316c662f7..174b4b9a2 100644 --- a/test_regress/t/t_gen_for.v +++ b/test_regress/t/t_gen_for.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_gen_for0.pl b/test_regress/t/t_gen_for0.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_gen_for0.pl +++ b/test_regress/t/t_gen_for0.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gen_for0.v b/test_regress/t/t_gen_for0.v index 79be997b7..1f5c8f239 100644 --- a/test_regress/t/t_gen_for0.v +++ b/test_regress/t/t_gen_for0.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -44,5 +43,5 @@ module Testit (clk); end end endgenerate - + endmodule diff --git a/test_regress/t/t_gen_for1.pl b/test_regress/t/t_gen_for1.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_gen_for1.pl +++ b/test_regress/t/t_gen_for1.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gen_for1.v b/test_regress/t/t_gen_for1.v index 3543e1cd1..17bc0b134 100644 --- a/test_regress/t/t_gen_for1.v +++ b/test_regress/t/t_gen_for1.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -64,7 +63,7 @@ module Testit (clk, reset, b); assign c[0] = my_sig; assign my_sig = 1'b1; -endmodule +endmodule module fnxtclk (u, reset, clk, w ); input u; @@ -79,7 +78,7 @@ module fnxtclk (u, reset, clk, w ); else begin w <= u; end - end + end -endmodule +endmodule diff --git a/test_regress/t/t_gen_forif.pl b/test_regress/t/t_gen_forif.pl index e0edd0ab2..9472f167f 100755 --- a/test_regress/t/t_gen_forif.pl +++ b/test_regress/t/t_gen_forif.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gen_forif.v b/test_regress/t/t_gen_forif.v index 2f188a698..6e542f089 100644 --- a/test_regress/t/t_gen_forif.v +++ b/test_regress/t/t_gen_forif.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -63,7 +62,7 @@ module Test (clk, Value, Result); reg Internal; assign Result = Internal ^ clk; - + always @(posedge clk) Internal <= #1 Value; endmodule @@ -75,7 +74,7 @@ module Test_wrap1 (clk, Value, Result); Test t (clk, Value, Result); endmodule - + module Test_wrap2 (clk, Value, Result); input clk; input Value; diff --git a/test_regress/t/t_gen_if.pl b/test_regress/t/t_gen_if.pl index 7ee6c5d6e..b0461556d 100755 --- a/test_regress/t/t_gen_if.pl +++ b/test_regress/t/t_gen_if.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gen_if.v b/test_regress/t/t_gen_if.v index d42b54ea1..bc6d4c3ca 100644 --- a/test_regress/t/t_gen_if.v +++ b/test_regress/t/t_gen_if.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // simplistic example, should choose 1st conditional generate and assign straight through // the tool also compiles the special case and determines an error (replication value is 0) diff --git a/test_regress/t/t_gen_intdot.pl b/test_regress/t/t_gen_intdot.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_gen_intdot.pl +++ b/test_regress/t/t_gen_intdot.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gen_intdot.v b/test_regress/t/t_gen_intdot.v index 752ef096b..1218bf9dc 100644 --- a/test_regress/t/t_gen_intdot.v +++ b/test_regress/t/t_gen_intdot.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_gen_intdot2.pl b/test_regress/t/t_gen_intdot2.pl index 5627aadc7..e2a0c97fa 100755 --- a/test_regress/t/t_gen_intdot2.pl +++ b/test_regress/t/t_gen_intdot2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id: t_gen_intdot.pl 837 2006-12-12 18:25:33Z wsnyder $ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gen_intdot2.v b/test_regress/t/t_gen_intdot2.v index 620626adb..f67053f8e 100644 --- a/test_regress/t/t_gen_intdot2.v +++ b/test_regress/t/t_gen_intdot2.v @@ -1,4 +1,3 @@ -// $Id: t_gen_intdot.v 840 2006-12-18 18:14:53Z wsnyder $ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_gen_var_bad.pl b/test_regress/t/t_gen_var_bad.pl index 0b0b4da7d..16ea21587 100755 --- a/test_regress/t/t_gen_var_bad.pl +++ b/test_regress/t/t_gen_var_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_gen_var_bad.v b/test_regress/t/t_gen_var_bad.v index 7cfb50493..7bb80e7da 100644 --- a/test_regress/t/t_gen_var_bad.v +++ b/test_regress/t/t_gen_var_bad.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_help.pl b/test_regress/t/t_help.pl index 24b50096e..325f056ce 100755 --- a/test_regress/t/t_help.pl +++ b/test_regress/t/t_help.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_if_deep.pl b/test_regress/t/t_if_deep.pl index c28ca5f05..af7c05a7b 100755 --- a/test_regress/t/t_if_deep.pl +++ b/test_regress/t/t_if_deep.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_if_deep.v b/test_regress/t/t_if_deep.v index e55aae8a6..2cdf4a87e 100644 --- a/test_regress/t/t_if_deep.v +++ b/test_regress/t/t_if_deep.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -71,7 +70,7 @@ module Test (/*AUTOARG*/ ); input clk; - input [31:0] in; + input [31:0] in; output [31:0] out; /*AUTOREG*/ diff --git a/test_regress/t/t_init_concat.pl b/test_regress/t/t_init_concat.pl index eff491d7a..2b6dd79c0 100755 --- a/test_regress/t/t_init_concat.pl +++ b/test_regress/t/t_init_concat.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_init_concat.v b/test_regress/t/t_init_concat.v index d7b20b0e4..4629ae2a4 100644 --- a/test_regress/t/t_init_concat.v +++ b/test_regress/t/t_init_concat.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -80,7 +79,7 @@ module regfile ( rd_data[0], 1'b1 }; - + assign rd_guardsok[0] = 1'b1; assign rd_guardsok[1] = rd_data[0]; diff --git a/test_regress/t/t_inst_array.v b/test_regress/t/t_inst_array.v index 26aafc41e..79e3c7645 100644 --- a/test_regress/t/t_inst_array.v +++ b/test_regress/t/t_inst_array.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_inst_array_bad.pl b/test_regress/t/t_inst_array_bad.pl index 9678a99b7..12bbaa1e9 100755 --- a/test_regress/t/t_inst_array_bad.pl +++ b/test_regress/t/t_inst_array_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can @@ -11,7 +10,7 @@ compile ( v_flags2 => ["--lint-only"], fails=>1, expect=> -'%Error: t/t_inst_array_bad.v:19: Port connection __pinNumber2 as part of a module instance array requires 1 or 8 bits, but connection\'s VARREF generates 9 bits. +'%Error: t/t_inst_array_bad.v:\d+: Port connection __pinNumber2 as part of a module instance array requires 1 or 8 bits, but connection\'s VARREF generates 9 bits. %Error: Exiting due to.*', ); diff --git a/test_regress/t/t_inst_array_bad.v b/test_regress/t/t_inst_array_bad.v index 8cffa9599..0517a15a0 100644 --- a/test_regress/t/t_inst_array_bad.v +++ b/test_regress/t/t_inst_array_bad.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_inst_array_inl0.pl b/test_regress/t/t_inst_array_inl0.pl index 55c797f57..cbc280c2c 100644 --- a/test_regress/t/t_inst_array_inl0.pl +++ b/test_regress/t/t_inst_array_inl0.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_array_inl1.pl b/test_regress/t/t_inst_array_inl1.pl index bb238c8b7..38ee74025 100755 --- a/test_regress/t/t_inst_array_inl1.pl +++ b/test_regress/t/t_inst_array_inl1.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_ccall.pl b/test_regress/t/t_inst_ccall.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_inst_ccall.pl +++ b/test_regress/t/t_inst_ccall.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_ccall.v b/test_regress/t/t_inst_ccall.v index 78e2be99e..68b307d29 100644 --- a/test_regress/t/t_inst_ccall.v +++ b/test_regress/t/t_inst_ccall.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_inst_mnpipe.pl b/test_regress/t/t_inst_mnpipe.pl index 456c64582..ebda975a0 100755 --- a/test_regress/t/t_inst_mnpipe.pl +++ b/test_regress/t/t_inst_mnpipe.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_mnpipe.v b/test_regress/t/t_inst_mnpipe.v index 3a29ee68f..4d4973aca 100644 --- a/test_regress/t/t_inst_mnpipe.v +++ b/test_regress/t/t_inst_mnpipe.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_inst_overwide.pl b/test_regress/t/t_inst_overwide.pl index 828380760..c2c8e3998 100755 --- a/test_regress/t/t_inst_overwide.pl +++ b/test_regress/t/t_inst_overwide.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_overwide.v b/test_regress/t/t_inst_overwide.v index 9b06586d3..85d4b8b32 100644 --- a/test_regress/t/t_inst_overwide.v +++ b/test_regress/t/t_inst_overwide.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t (/*AUTOARG*/ // Outputs - outc_w30, outd_w73, + outc_w30, outd_w73, // Inputs clk, ina_w1, inb_w61 ); @@ -32,7 +31,7 @@ endmodule module sub (/*AUTOARG*/ // Outputs - outy_w92, outz_w22, + outy_w92, outz_w22, // Inputs clk, inw_w31, inx_w11 ); diff --git a/test_regress/t/t_inst_overwide_bad.pl b/test_regress/t/t_inst_overwide_bad.pl index a649b858f..48769479f 100755 --- a/test_regress/t/t_inst_overwide_bad.pl +++ b/test_regress/t/t_inst_overwide_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_recurse_bad.pl b/test_regress/t/t_inst_recurse_bad.pl index 89513f124..788af57f4 100755 --- a/test_regress/t/t_inst_recurse_bad.pl +++ b/test_regress/t/t_inst_recurse_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can @@ -10,7 +9,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } compile ( fails=>1, expect=> -'.*%Error: t/t_inst_recurse_bad.v:18: Recursive module .module instantiates itself.: looped +'.*%Error: t/t_inst_recurse_bad.v:\d+: Recursive module .module instantiates itself.: looped %Error: Exiting due to.*', ); diff --git a/test_regress/t/t_inst_recurse_bad.v b/test_regress/t/t_inst_recurse_bad.v index fdf05aba4..f0a28be7f 100644 --- a/test_regress/t/t_inst_recurse_bad.v +++ b/test_regress/t/t_inst_recurse_bad.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_inst_sv.pl b/test_regress/t/t_inst_sv.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_inst_sv.pl +++ b/test_regress/t/t_inst_sv.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_sv.v b/test_regress/t/t_inst_sv.v index fe704a46c..663569209 100644 --- a/test_regress/t/t_inst_sv.v +++ b/test_regress/t/t_inst_sv.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_inst_tree.v b/test_regress/t/t_inst_tree.v index a288de288..976578848 100644 --- a/test_regress/t/t_inst_tree.v +++ b/test_regress/t/t_inst_tree.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_inst_tree_inl0_pub0.pl b/test_regress/t/t_inst_tree_inl0_pub0.pl index 45149f2b1..373d05de4 100755 --- a/test_regress/t/t_inst_tree_inl0_pub0.pl +++ b/test_regress/t/t_inst_tree_inl0_pub0.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_tree_inl0_pub1.pl b/test_regress/t/t_inst_tree_inl0_pub1.pl index 4682a2ab5..678f2ab5e 100755 --- a/test_regress/t/t_inst_tree_inl0_pub1.pl +++ b/test_regress/t/t_inst_tree_inl0_pub1.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_tree_inl1_pub0.pl b/test_regress/t/t_inst_tree_inl1_pub0.pl index a92046c4d..85b32b96c 100755 --- a/test_regress/t/t_inst_tree_inl1_pub0.pl +++ b/test_regress/t/t_inst_tree_inl1_pub0.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_tree_inl1_pub1.pl b/test_regress/t/t_inst_tree_inl1_pub1.pl index 1afc4b8f9..f258b632a 100755 --- a/test_regress/t/t_inst_tree_inl1_pub1.pl +++ b/test_regress/t/t_inst_tree_inl1_pub1.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_v2k.pl b/test_regress/t/t_inst_v2k.pl index 9bee77438..b4ad6095a 100755 --- a/test_regress/t/t_inst_v2k.pl +++ b/test_regress/t/t_inst_v2k.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_v2k.v b/test_regress/t/t_inst_v2k.v index 7e7f00f8f..3cad02087 100644 --- a/test_regress/t/t_inst_v2k.v +++ b/test_regress/t/t_inst_v2k.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_inst_v2k_sub.vi b/test_regress/t/t_inst_v2k_sub.vi index 3194501ab..631e42489 100644 --- a/test_regress/t/t_inst_v2k_sub.vi +++ b/test_regress/t/t_inst_v2k_sub.vi @@ -1,4 +1,4 @@ -// $Id$ -*- Verilog -*- +// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_inst_wideconst.pl b/test_regress/t/t_inst_wideconst.pl index 3c1520a21..2472d705f 100755 --- a/test_regress/t/t_inst_wideconst.pl +++ b/test_regress/t/t_inst_wideconst.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_inst_wideconst.v b/test_regress/t/t_inst_wideconst.v index 3258f12d5..5e8423576 100644 --- a/test_regress/t/t_inst_wideconst.v +++ b/test_regress/t/t_inst_wideconst.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_leak.cpp b/test_regress/t/t_leak.cpp index 3c0f01a1c..067e831bb 100644 --- a/test_regress/t/t_leak.cpp +++ b/test_regress/t/t_leak.cpp @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test driver/expect definition // // Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_leak.pl b/test_regress/t/t_leak.pl index 401bfcafa..95bc24bcd 100755 --- a/test_regress/t/t_leak.pl +++ b/test_regress/t/t_leak.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_leak.v b/test_regress/t/t_leak.v index 631c154ad..667d998c8 100644 --- a/test_regress/t/t_leak.v +++ b/test_regress/t/t_leak.v @@ -1,11 +1,10 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2006 by Wilson Snyder. module t (clk); - + sub sub (); input clk; diff --git a/test_regress/t/t_lint_implicit.pl b/test_regress/t/t_lint_implicit.pl index 91837914b..5d05b50ab 100755 --- a/test_regress/t/t_lint_implicit.pl +++ b/test_regress/t/t_lint_implicit.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_lint_implicit.v b/test_regress/t/t_lint_implicit.v index 3a8e3b24c..9445d0914 100644 --- a/test_regress/t/t_lint_implicit.v +++ b/test_regress/t/t_lint_implicit.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_lint_implicit_bad.pl b/test_regress/t/t_lint_implicit_bad.pl index 17686cb53..21cf86e9f 100755 --- a/test_regress/t/t_lint_implicit_bad.pl +++ b/test_regress/t/t_lint_implicit_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_lint_only.pl b/test_regress/t/t_lint_only.pl index 791baab1d..e0816d0cb 100755 --- a/test_regress/t/t_lint_only.pl +++ b/test_regress/t/t_lint_only.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_lint_only.v b/test_regress/t/t_lint_only.v index f2fa2c0cb..ce955f7ce 100644 --- a/test_regress/t/t_lint_only.v +++ b/test_regress/t/t_lint_only.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_lint_restore_bad.pl b/test_regress/t/t_lint_restore_bad.pl index 6b97f3faf..70fec0ea7 100755 --- a/test_regress/t/t_lint_restore_bad.pl +++ b/test_regress/t/t_lint_restore_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_lint_restore_bad.v b/test_regress/t/t_lint_restore_bad.v index 8423ad8bb..7f2637557 100644 --- a/test_regress/t/t_lint_restore_bad.v +++ b/test_regress/t/t_lint_restore_bad.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_math_clog2.pl b/test_regress/t/t_math_clog2.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_math_clog2.pl +++ b/test_regress/t/t_math_clog2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_clog2.v b/test_regress/t/t_math_clog2.v index 2ce5dba94..2f65856ac 100644 --- a/test_regress/t/t_math_clog2.v +++ b/test_regress/t/t_math_clog2.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_math_cmp.pl b/test_regress/t/t_math_cmp.pl index 7e6b144bc..e2a0c97fa 100755 --- a/test_regress/t/t_math_cmp.pl +++ b/test_regress/t/t_math_cmp.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Revision: 1.1 $$Date$$Author$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_cmp.v b/test_regress/t/t_math_cmp.v index 0eb04de62..6402e205f 100644 --- a/test_regress/t/t_math_cmp.v +++ b/test_regress/t/t_math_cmp.v @@ -1,4 +1,3 @@ -// $Revision: 1.1 $$Date$$Author$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -163,5 +162,5 @@ module prover ( results[4][3] = 8'b0_0_0_0_1_1_1_1; results[4][4] = 8'b0_0_1_1_0_0_1_1; end - + endmodule diff --git a/test_regress/t/t_math_concat.pl b/test_regress/t/t_math_concat.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_math_concat.pl +++ b/test_regress/t/t_math_concat.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_concat.v b/test_regress/t/t_math_concat.v index f0d5679ea..7a6a79ff6 100644 --- a/test_regress/t/t_math_concat.v +++ b/test_regress/t/t_math_concat.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -49,7 +48,7 @@ module t (/*AUTOARG*/ i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] }; - + always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; diff --git a/test_regress/t/t_math_concat64.pl b/test_regress/t/t_math_concat64.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_math_concat64.pl +++ b/test_regress/t/t_math_concat64.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_concat64.v b/test_regress/t/t_math_concat64.v index 59f804cf7..f40739b42 100644 --- a/test_regress/t/t_math_concat64.v +++ b/test_regress/t/t_math_concat64.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -38,7 +37,7 @@ module t (/*AUTOARG*/ i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; - + assign q64[127:64] = { i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], @@ -59,7 +58,7 @@ module t (/*AUTOARG*/ i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; - + assign q64_low = { i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], @@ -91,7 +90,7 @@ module t (/*AUTOARG*/ i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; - + always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; diff --git a/test_regress/t/t_math_const.pl b/test_regress/t/t_math_const.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_math_const.pl +++ b/test_regress/t/t_math_const.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_const.v b/test_regress/t/t_math_const.v index 3e0557782..5bc7f2073 100644 --- a/test_regress/t/t_math_const.v +++ b/test_regress/t/t_math_const.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -48,7 +47,7 @@ module t (/*AUTOARG*/ if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop; $display("%x %x %x\n", con2, con2[31:0], con2[39:32]); if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop; - if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop; + if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop; // verilator lint_off WIDTH con1 = 10'h10 + 40'h80_1100_0131; @@ -60,7 +59,7 @@ module t (/*AUTOARG*/ // verilator lint_off WIDTH conw3 = 94'h000a_5010_4020_3030_2040_1050; // verilator lint_on WIDTH - if (conw3[31:00]!== 32'h2040_1050 || + if (conw3[31:00]!== 32'h2040_1050 || conw3[63:32]!== 32'h4020_3030 || conw3[95:64]!== 32'h000a_5010 || conw3[128:96]!==33'h0) $stop; @@ -71,7 +70,7 @@ module t (/*AUTOARG*/ // verilator lint_off WIDTH conw4 = 112'h7010_602a_5030_4040_3050_2060_1070; // verilator lint_on WIDTH - if (conw4[31:00]!== 32'h2060_1070 || + if (conw4[31:00]!== 32'h2060_1070 || conw4[63:32]!== 32'h4040_3050 || conw4[95:64]!== 32'h602a_5030 || conw4[127:96]!==32'h7010) $stop; diff --git a/test_regress/t/t_math_div.pl b/test_regress/t/t_math_div.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_math_div.pl +++ b/test_regress/t/t_math_div.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_div.v b/test_regress/t/t_math_div.v index 6ecac51b6..46d05411a 100644 --- a/test_regress/t/t_math_div.v +++ b/test_regress/t/t_math_div.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -24,7 +23,7 @@ module t (/*AUTOARG*/ qqs = $signed(a[60:0]) / $signed(divisor); rqs = $signed(a[60:0]) % $signed(divisor); end - + integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin diff --git a/test_regress/t/t_math_eq.pl b/test_regress/t/t_math_eq.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_math_eq.pl +++ b/test_regress/t/t_math_eq.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_eq.v b/test_regress/t/t_math_eq.v index 4f9d16c88..dad6aeab8 100644 --- a/test_regress/t/t_math_eq.v +++ b/test_regress/t/t_math_eq.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -71,7 +70,7 @@ module Test (/*AUTOARG*/ ); input clk; - input [31:0] in; + input [31:0] in; output [3:0] out; assign out[0] = in[3:0] ==? 4'b1001; diff --git a/test_regress/t/t_math_equal.pl b/test_regress/t/t_math_equal.pl index c4aacfed8..2b6dd79c0 100755 --- a/test_regress/t/t_math_equal.pl +++ b/test_regress/t/t_math_equal.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_equal.v b/test_regress/t/t_math_equal.v index 9bb9300d1..437bd0f6e 100644 --- a/test_regress/t/t_math_equal.v +++ b/test_regress/t/t_math_equal.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -12,7 +11,7 @@ module t (/*AUTOARG*/ input clk; integer _mode; - + reg _guard1; reg [127:0] r_wide0; reg _guard2; diff --git a/test_regress/t/t_math_imm.pl b/test_regress/t/t_math_imm.pl index c28ca5f05..af7c05a7b 100755 --- a/test_regress/t/t_math_imm.pl +++ b/test_regress/t/t_math_imm.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_imm.v b/test_regress/t/t_math_imm.v index 9bebcae4f..9c178ec39 100644 --- a/test_regress/t/t_math_imm.v +++ b/test_regress/t/t_math_imm.v @@ -1,10 +1,9 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2005 by Wilson Snyder. // -// Example module to create problem. +// Example module to create problem. // // generate a 64 bit value with bits // [HighMaskSel_Bot : LowMaskSel_Bot ] = 1 diff --git a/test_regress/t/t_math_imm2.cpp b/test_regress/t/t_math_imm2.cpp index cc9e7c910..c0027b35f 100644 --- a/test_regress/t/t_math_imm2.cpp +++ b/test_regress/t/t_math_imm2.cpp @@ -30,8 +30,8 @@ int main (int argc, char *argv[]) { | MaskVal (sim->LowMaskSel_Bot, sim->HighMaskSel_Bot); if (sim->LogicImm != expected) { - printf ("%%Error: %d.%d,%d.%d -> %016llx/%016llx -> %016llx (expected %016llx)\n", - sim->LowMaskSel_Top, sim->HighMaskSel_Top, + printf ("%%Error: %d.%d,%d.%d -> %016llx/%016llx -> %016llx (expected %016llx)\n", + sim->LowMaskSel_Top, sim->HighMaskSel_Top, sim->LowMaskSel_Bot, sim->HighMaskSel_Bot, sim->LowLogicImm, sim->HighLogicImm, sim->LogicImm, expected); diff --git a/test_regress/t/t_math_imm2.pl b/test_regress/t/t_math_imm2.pl index 7ffe31944..0e05c6fa6 100755 --- a/test_regress/t/t_math_imm2.pl +++ b/test_regress/t/t_math_imm2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_imm2.v b/test_regress/t/t_math_imm2.v index 02af75dfa..3e31ad724 100644 --- a/test_regress/t/t_math_imm2.v +++ b/test_regress/t/t_math_imm2.v @@ -1,10 +1,9 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2005 by Wilson Snyder. // -// Example module to create problem. +// Example module to create problem. // // generate a 64 bit value with bits // [HighMaskSel_Bot : LowMaskSel_Bot ] = 1 diff --git a/test_regress/t/t_math_mul.pl b/test_regress/t/t_math_mul.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_math_mul.pl +++ b/test_regress/t/t_math_mul.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_mul.v b/test_regress/t/t_math_mul.v index 3b6d408b1..5f987eced 100644 --- a/test_regress/t/t_math_mul.v +++ b/test_regress/t/t_math_mul.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -61,12 +60,12 @@ module sub (/*AUTOARG*/ input [15:0] in2; output reg signed [31:0] out1; output reg unsigned [31:0] out2; - + always @* begin // verilator lint_off WIDTH out1 = $signed(in1) * $signed(in2); out2 = $unsigned(in1) * $unsigned(in2); // verilator lint_on WIDTH end - + endmodule diff --git a/test_regress/t/t_math_pow.pl b/test_regress/t/t_math_pow.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_math_pow.pl +++ b/test_regress/t/t_math_pow.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_pow.v b/test_regress/t/t_math_pow.v index e276e17e5..49839e13a 100644 --- a/test_regress/t/t_math_pow.v +++ b/test_regress/t/t_math_pow.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -20,7 +19,7 @@ module t (/*AUTOARG*/ p = a[60:0] ** b[20:0]; shifted = 2 ** b[20:0]; end - + integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin diff --git a/test_regress/t/t_math_repl.pl b/test_regress/t/t_math_repl.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_math_repl.pl +++ b/test_regress/t/t_math_repl.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_repl.v b/test_regress/t/t_math_repl.v index 35c5b650b..1cecfe26d 100644 --- a/test_regress/t/t_math_repl.v +++ b/test_regress/t/t_math_repl.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -32,24 +31,24 @@ module t (/*AUTOARG*/ | ( {{16{src0[31]}}, {16{src0[15]}}} & {2{~mask[31:16]}}))); - wire [31:0] sl_mask + wire [31:0] sl_mask = (32'hffffffff << src1[4:0]); - - wire [31:0] sr_mask + + wire [31:0] sr_mask = {sl_mask[0], sl_mask[1], - sl_mask[2], sl_mask[3], sl_mask[4], + sl_mask[2], sl_mask[3], sl_mask[4], sl_mask[5], sl_mask[6], sl_mask[7], - sl_mask[8], sl_mask[9], + sl_mask[8], sl_mask[9], sl_mask[10], sl_mask[11], - sl_mask[12], sl_mask[13], sl_mask[14], + sl_mask[12], sl_mask[13], sl_mask[14], sl_mask[15], sl_mask[16], - sl_mask[17], sl_mask[18], sl_mask[19], + sl_mask[17], sl_mask[18], sl_mask[19], sl_mask[20], sl_mask[21], - sl_mask[22], sl_mask[23], sl_mask[24], + sl_mask[22], sl_mask[23], sl_mask[24], sl_mask[25], sl_mask[26], sl_mask[27], sl_mask[28], sl_mask[29], sl_mask[30], sl_mask[31]}; - + always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; diff --git a/test_regress/t/t_math_reverse.pl b/test_regress/t/t_math_reverse.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_math_reverse.pl +++ b/test_regress/t/t_math_reverse.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_reverse.v b/test_regress/t/t_math_reverse.v index 1bc3a603d..90bebd553 100644 --- a/test_regress/t/t_math_reverse.v +++ b/test_regress/t/t_math_reverse.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_math_shift.pl b/test_regress/t/t_math_shift.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_math_shift.pl +++ b/test_regress/t/t_math_shift.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_shift.v b/test_regress/t/t_math_shift.v index ed9c6829e..3069a3d40 100644 --- a/test_regress/t/t_math_shift.v +++ b/test_regress/t/t_math_shift.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -23,7 +22,7 @@ module t (/*AUTOARG*/ qright = 64'hf784bf8f_12734089 >> amt; qleft = 64'hf784bf8f_12734089 >> amt; end - + integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin diff --git a/test_regress/t/t_math_shiftrs.pl b/test_regress/t/t_math_shiftrs.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_math_shiftrs.pl +++ b/test_regress/t/t_math_shiftrs.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_shiftrs.v b/test_regress/t/t_math_shiftrs.v index edc530990..3248a9412 100644 --- a/test_regress/t/t_math_shiftrs.v +++ b/test_regress/t/t_math_shiftrs.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_math_signed.pl b/test_regress/t/t_math_signed.pl index ffce37ad9..857d38574 100755 --- a/test_regress/t/t_math_signed.pl +++ b/test_regress/t/t_math_signed.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Revision: 1.1 $$Date$$Author$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_signed.v b/test_regress/t/t_math_signed.v index cba3253b7..5a0634a6c 100644 --- a/test_regress/t/t_math_signed.v +++ b/test_regress/t/t_math_signed.v @@ -1,4 +1,3 @@ -// $Revision: 1.1 $$Date$$Author$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -40,7 +39,7 @@ module t (/*AUTOARG*/ b_us = b[4:0]>>>4; // Unsigned, due to extract // verilator lint_on WIDTH end - + integer i; initial begin if ((-1 >>> 3) != -1) $stop; // Decimals are signed diff --git a/test_regress/t/t_math_signed2.pl b/test_regress/t/t_math_signed2.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_math_signed2.pl +++ b/test_regress/t/t_math_signed2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_signed2.v b/test_regress/t/t_math_signed2.v index 286e6f423..1250f9922 100644 --- a/test_regress/t/t_math_signed2.v +++ b/test_regress/t/t_math_signed2.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -19,7 +18,7 @@ module t (/*AUTOARG*/ initial begin in = 11'b10000001000; - for(k=0;k<32;k=k+1) + for(k=0;k<32;k=k+1) delay_minmax[k] = 0; end diff --git a/test_regress/t/t_math_svl.pl b/test_regress/t/t_math_svl.pl index ce8d370c2..29e9c7874 100755 --- a/test_regress/t/t_math_svl.pl +++ b/test_regress/t/t_math_svl.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2005 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_svl.v b/test_regress/t/t_math_svl.v index 890da8670..5e4256fe3 100644 --- a/test_regress/t/t_math_svl.v +++ b/test_regress/t/t_math_svl.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -35,7 +34,7 @@ module t (/*AUTOARG*/ qo = $onehot(q); q0 = $onehot0(q); end - + integer cyc; initial cyc=1; always_ff @ (posedge clk) begin if (cyc!=0) begin diff --git a/test_regress/t/t_math_svl2.pl b/test_regress/t/t_math_svl2.pl index 908ee10cd..b19314663 100755 --- a/test_regress/t/t_math_svl2.pl +++ b/test_regress/t/t_math_svl2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2006 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_svl2.v b/test_regress/t/t_math_svl2.v index 4db302ed8..a667dabd4 100644 --- a/test_regress/t/t_math_svl2.v +++ b/test_regress/t/t_math_svl2.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_math_swap.pl b/test_regress/t/t_math_swap.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_math_swap.pl +++ b/test_regress/t/t_math_swap.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_swap.v b/test_regress/t/t_math_swap.v index d45ca54fa..96daf421d 100644 --- a/test_regress/t/t_math_swap.v +++ b/test_regress/t/t_math_swap.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_math_tri.pl b/test_regress/t/t_math_tri.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_math_tri.pl +++ b/test_regress/t/t_math_tri.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_tri.v b/test_regress/t/t_math_tri.v index ccfc259ba..96a873716 100644 --- a/test_regress/t/t_math_tri.v +++ b/test_regress/t/t_math_tri.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_math_vgen.pl b/test_regress/t/t_math_vgen.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_math_vgen.pl +++ b/test_regress/t/t_math_vgen.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_vgen.v b/test_regress/t/t_math_vgen.v index 8991911f6..d5eb09c1c 100644 --- a/test_regress/t/t_math_vgen.v +++ b/test_regress/t/t_math_vgen.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -79,7 +78,7 @@ module t (/*AUTOARG*/ if ((W0420[(- (W0421[115:110]))]) != (1'h1)) if (check) $stop; end end - + //============================================================ // gcc_2_96_bug @@ -115,7 +114,7 @@ module t (/*AUTOARG*/ if (((W0592[119:9]) >> ((W0593))) != (111'h0000000000000000000000000000)) if (check) $stop; end end - + //============================================================ reg [127:0] WA1063 ; //=00000000000000000000000000000001 diff --git a/test_regress/t/t_math_vliw.pl b/test_regress/t/t_math_vliw.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_math_vliw.pl +++ b/test_regress/t/t_math_vliw.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_math_vliw.v b/test_regress/t/t_math_vliw.v index 2a13f76a8..19ac6136c 100644 --- a/test_regress/t/t_math_vliw.v +++ b/test_regress/t/t_math_vliw.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_mem.pl b/test_regress/t/t_mem.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_mem.pl +++ b/test_regress/t/t_mem.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem.v b/test_regress/t/t_mem.v index 64cc93159..341a8b703 100644 --- a/test_regress/t/t_mem.v +++ b/test_regress/t/t_mem.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -26,7 +25,7 @@ module t (/*AUTOARG*/ memory8_16[{m_addr,1'd0}]} <= m_data; end end - + reg [7:0] memory8_16_4; reg [7:0] memory8_16_5; // Test complicated sensitivity lists diff --git a/test_regress/t/t_mem_fifo.pl b/test_regress/t/t_mem_fifo.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_mem_fifo.pl +++ b/test_regress/t/t_mem_fifo.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_fifo.v b/test_regress/t/t_mem_fifo.v index 071c70b5d..a7285273d 100644 --- a/test_regress/t/t_mem_fifo.v +++ b/test_regress/t/t_mem_fifo.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -85,7 +84,7 @@ module fifo (/*AUTOARG*/ output [65:0] outData; input wrEn; - + reg [65:0] outData; reg [65:0] fifo[0:fifoDepth-1]; diff --git a/test_regress/t/t_mem_file.pl b/test_regress/t/t_mem_file.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_mem_file.pl +++ b/test_regress/t/t_mem_file.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_file.v b/test_regress/t/t_mem_file.v index 05edda729..9d8af048d 100644 --- a/test_regress/t/t_mem_file.v +++ b/test_regress/t/t_mem_file.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -80,7 +79,7 @@ module file (/*AUTOARG*/ // Inputs clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d ); - + input clk; input r1_en; input [1:0] r1_ad; @@ -94,7 +93,7 @@ module file (/*AUTOARG*/ input w2_en; input [1:0] w2_a; input [63:0] w2_d; - + /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) // End of automatics @@ -114,7 +113,7 @@ module file (/*AUTOARG*/ wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d; wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe; - + // Storage reg [63:0] m_rg0_r; reg [63:0] m_rg1_r; diff --git a/test_regress/t/t_mem_iforder.pl b/test_regress/t/t_mem_iforder.pl index 456c64582..ebda975a0 100755 --- a/test_regress/t/t_mem_iforder.pl +++ b/test_regress/t/t_mem_iforder.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_iforder.v b/test_regress/t/t_mem_iforder.v index f8c065382..3a669005f 100644 --- a/test_regress/t/t_mem_iforder.v +++ b/test_regress/t/t_mem_iforder.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -72,7 +71,7 @@ module fifo (/*AUTOARG*/ output [15:0] out0; output [15:0] out1; - + reg [15:0] mem [1:0]; reg [15:0] memtemp2 [1:0]; reg [15:0] memtemp3 [1:0]; diff --git a/test_regress/t/t_mem_multi_io_bad.pl b/test_regress/t/t_mem_multi_io_bad.pl index c000a520f..6fbec6f91 100755 --- a/test_regress/t/t_mem_multi_io_bad.pl +++ b/test_regress/t/t_mem_multi_io_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_multi_io_bad.v b/test_regress/t/t_mem_multi_io_bad.v index 429a7526d..1e651f688 100644 --- a/test_regress/t/t_mem_multi_io_bad.v +++ b/test_regress/t/t_mem_multi_io_bad.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_mem_multi_ref_bad.pl b/test_regress/t/t_mem_multi_ref_bad.pl index 21012cdec..12fe61f60 100755 --- a/test_regress/t/t_mem_multi_ref_bad.pl +++ b/test_regress/t/t_mem_multi_ref_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_multi_ref_bad.v b/test_regress/t/t_mem_multi_ref_bad.v index ed8449042..a9c33df26 100644 --- a/test_regress/t/t_mem_multi_ref_bad.v +++ b/test_regress/t/t_mem_multi_ref_bad.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -18,6 +17,6 @@ module t (/*AUTOARG*/); dim0nv[1:0] = 0; // Bad: Not vectored dim0nv[1][1] = 0; // Bad: Not arrayed to right depth end - + endmodule diff --git a/test_regress/t/t_mem_multidim.pl b/test_regress/t/t_mem_multidim.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_mem_multidim.pl +++ b/test_regress/t/t_mem_multidim.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_multidim.v b/test_regress/t/t_mem_multidim.v index e9c4d56ca..88233d186 100644 --- a/test_regress/t/t_mem_multidim.v +++ b/test_regress/t/t_mem_multidim.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_mem_multidim_Ox.pl b/test_regress/t/t_mem_multidim_Ox.pl index 0dcbe349b..96d671998 100755 --- a/test_regress/t/t_mem_multidim_Ox.pl +++ b/test_regress/t/t_mem_multidim_Ox.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_multidim_trace.pl b/test_regress/t/t_mem_multidim_trace.pl index 875cf56fa..83a8f701f 100755 --- a/test_regress/t/t_mem_multidim_trace.pl +++ b/test_regress/t/t_mem_multidim_trace.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_multiwire.pl b/test_regress/t/t_mem_multiwire.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_mem_multiwire.pl +++ b/test_regress/t/t_mem_multiwire.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_multiwire.v b/test_regress/t/t_mem_multiwire.v index e04d6362a..c9cfcb90a 100644 --- a/test_regress/t/t_mem_multiwire.v +++ b/test_regress/t/t_mem_multiwire.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_mem_shift.pl b/test_regress/t/t_mem_shift.pl index 7b2256408..eee6f047f 100755 --- a/test_regress/t/t_mem_shift.pl +++ b/test_regress/t/t_mem_shift.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_shift.v b/test_regress/t/t_mem_shift.v index 939c2492f..9d2ee0f1e 100644 --- a/test_regress/t/t_mem_shift.v +++ b/test_regress/t/t_mem_shift.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_mem_slot.pl b/test_regress/t/t_mem_slot.pl index 401bfcafa..95bc24bcd 100755 --- a/test_regress/t/t_mem_slot.pl +++ b/test_regress/t/t_mem_slot.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mem_slot.v b/test_regress/t/t_mem_slot.v index 9c5805185..94a6db4bb 100644 --- a/test_regress/t/t_mem_slot.v +++ b/test_regress/t/t_mem_slot.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -7,14 +6,14 @@ `define RegDel 1 module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal); - + input Clk; input [1:0] SlotIdx; input BitToChange; input BitVal; input [1:0] SlotToReturn; output [1:0] OutputVal; - + reg [1:0] Array[0:2]; always @(posedge Clk) diff --git a/test_regress/t/t_mod_dup_bad.pl b/test_regress/t/t_mod_dup_bad.pl index 3803c9144..972360975 100755 --- a/test_regress/t/t_mod_dup_bad.pl +++ b/test_regress/t/t_mod_dup_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_mod_dup_bad.v b/test_regress/t/t_mod_dup_bad.v index a139be462..296f098ac 100644 --- a/test_regress/t/t_mod_dup_bad.v +++ b/test_regress/t/t_mod_dup_bad.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_order.pl b/test_regress/t/t_order.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_order.pl +++ b/test_regress/t/t_order.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_order.v b/test_regress/t/t_order.v index 157f356c9..84fbedad8 100644 --- a/test_regress/t/t_order.v +++ b/test_regress/t/t_order.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -9,8 +8,8 @@ module t (/*AUTOARG*/ clk ); - // surefire lint_off ASWEBB - // surefire lint_off ASWEMB + // surefire lint_off ASWEBB + // surefire lint_off ASWEMB // surefire lint_off STMINI // surefire lint_off CSEBEQ @@ -56,7 +55,7 @@ module t (/*AUTOARG*/ reg [7:0] o_from_com_levs12; reg [7:0] o_from_com_levs13; always @ (/*AS*/o_from_com_levs11) begin - o_from_com_levs12 = o_from_com_levs11 + 8'h1; + o_from_com_levs12 = o_from_com_levs11 + 8'h1; o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize o_from_com_levs13 = o_from_com_levs12; end diff --git a/test_regress/t/t_order_a.v b/test_regress/t/t_order_a.v index ac8d2e600..4f5062030 100644 --- a/test_regress/t/t_order_a.v +++ b/test_regress/t/t_order_a.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_order_a (/*AUTOARG*/ // Outputs - m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12, + m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12, // Inputs clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one ); @@ -27,8 +26,8 @@ module t_order_a (/*AUTOARG*/ reg [7:0] m_from_clk_lev1_r; // End of automatics - // surefire lint_off ASWEBB - // surefire lint_off ASWEMB + // surefire lint_off ASWEBB + // surefire lint_off ASWEMB wire [7:0] a_to_clk_levm1; wire [7:0] a_to_clk_levm2; diff --git a/test_regress/t/t_order_b.v b/test_regress/t/t_order_b.v index 82733512f..c19f566e2 100644 --- a/test_regress/t/t_order_b.v +++ b/test_regress/t/t_order_b.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_order_b (/*AUTOARG*/ // Outputs - o_subfrom_clk_lev2, + o_subfrom_clk_lev2, // Inputs m_from_clk_lev1_r ); diff --git a/test_regress/t/t_order_clkinst.pl b/test_regress/t/t_order_clkinst.pl index a9bd24155..7b54e1f21 100755 --- a/test_regress/t/t_order_clkinst.pl +++ b/test_regress/t/t_order_clkinst.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_order_clkinst.v b/test_regress/t/t_order_clkinst.v index 85e896ec4..ea2428e84 100644 --- a/test_regress/t/t_order_clkinst.v +++ b/test_regress/t/t_order_clkinst.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -17,7 +16,7 @@ module t (/*AUTOARG*/ reg c1_start; initial c1_start = 0; wire [31:0] c1_count; comb_loop c1 (.count(c1_count), .start(c1_start)); - + wire s2_start = (c1_count==0 && c1_start); wire [31:0] s2_count; seq_loop s2 (.count(s2_count), .start(s2_start)); diff --git a/test_regress/t/t_order_comboclkloop.pl b/test_regress/t/t_order_comboclkloop.pl index a9aa87fed..246d61589 100755 --- a/test_regress/t/t_order_comboclkloop.pl +++ b/test_regress/t/t_order_comboclkloop.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_order_comboclkloop.v b/test_regress/t/t_order_comboclkloop.v index c52bf5677..e750675a0 100644 --- a/test_regress/t/t_order_comboclkloop.v +++ b/test_regress/t/t_order_comboclkloop.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_order_comboloop.pl b/test_regress/t/t_order_comboloop.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_order_comboloop.pl +++ b/test_regress/t/t_order_comboloop.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_order_comboloop.v b/test_regress/t/t_order_comboloop.v index 5c695d027..b852991dc 100644 --- a/test_regress/t/t_order_comboloop.v +++ b/test_regress/t/t_order_comboloop.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_order_doubleloop.pl b/test_regress/t/t_order_doubleloop.pl index a9bd24155..7b54e1f21 100755 --- a/test_regress/t/t_order_doubleloop.pl +++ b/test_regress/t/t_order_doubleloop.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_order_doubleloop.v b/test_regress/t/t_order_doubleloop.v index 762dbf742..d8e172901 100644 --- a/test_regress/t/t_order_doubleloop.v +++ b/test_regress/t/t_order_doubleloop.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_order_multialways.pl b/test_regress/t/t_order_multialways.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_order_multialways.pl +++ b/test_regress/t/t_order_multialways.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_order_multialways.v b/test_regress/t/t_order_multialways.v index 3d3f8c27d..23e1626d1 100644 --- a/test_regress/t/t_order_multialways.v +++ b/test_regress/t/t_order_multialways.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_order_wireloop.pl b/test_regress/t/t_order_wireloop.pl index fdb4b5365..494a3f781 100755 --- a/test_regress/t/t_order_wireloop.pl +++ b/test_regress/t/t_order_wireloop.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2005 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_order_wireloop.v b/test_regress/t/t_order_wireloop.v index 6c5bc0128..1f4363ce3 100644 --- a/test_regress/t/t_order_wireloop.v +++ b/test_regress/t/t_order_wireloop.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_param.pl b/test_regress/t/t_param.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_param.pl +++ b/test_regress/t/t_param.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_param.v b/test_regress/t/t_param.v index ad55b3deb..3efd5ce32 100644 --- a/test_regress/t/t_param.v +++ b/test_regress/t/t_param.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -9,7 +8,7 @@ module t (/*AUTOARG*/ clk ); parameter PAR = 3; - + m1 #(PAR) m1(); m3 #(PAR) m3(); diff --git a/test_regress/t/t_param_concat.pl b/test_regress/t/t_param_concat.pl index d272045ca..9ff5da37b 100755 --- a/test_regress/t/t_param_concat.pl +++ b/test_regress/t/t_param_concat.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_param_concat.v b/test_regress/t/t_param_concat.v index 8f70dbf8d..b4300142a 100644 --- a/test_regress/t/t_param_concat.v +++ b/test_regress/t/t_param_concat.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_param_concat_bad.pl b/test_regress/t/t_param_concat_bad.pl index 9ec4860fa..e7ad1e2f0 100755 --- a/test_regress/t/t_param_concat_bad.pl +++ b/test_regress/t/t_param_concat_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_param_long.pl b/test_regress/t/t_param_long.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_param_long.pl +++ b/test_regress/t/t_param_long.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_param_long.v b/test_regress/t/t_param_long.v index 792da0b3c..ebf6c0a78 100644 --- a/test_regress/t/t_param_long.v +++ b/test_regress/t/t_param_long.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_param_named.pl b/test_regress/t/t_param_named.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_param_named.pl +++ b/test_regress/t/t_param_named.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_param_named.v b/test_regress/t/t_param_named.v index e474db7aa..bdbc2901b 100644 --- a/test_regress/t/t_param_named.v +++ b/test_regress/t/t_param_named.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_param_named_2.pl b/test_regress/t/t_param_named_2.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_param_named_2.pl +++ b/test_regress/t/t_param_named_2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_param_named_2.v b/test_regress/t/t_param_named_2.v index c06a093c9..f4e4126cd 100644 --- a/test_regress/t/t_param_named_2.v +++ b/test_regress/t/t_param_named_2.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_param_repl.pl b/test_regress/t/t_param_repl.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_param_repl.pl +++ b/test_regress/t/t_param_repl.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_param_repl.v b/test_regress/t/t_param_repl.v index 89483d8ef..4e71b3127 100644 --- a/test_regress/t/t_param_repl.v +++ b/test_regress/t/t_param_repl.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_pp_display.pl b/test_regress/t/t_pp_display.pl index d51bcd4ef..d4b442214 100755 --- a/test_regress/t/t_pp_display.pl +++ b/test_regress/t/t_pp_display.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id: t_delay.pl 965 2007-10-31 20:29:07Z wsnyder $ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_pp_display.v b/test_regress/t/t_pp_display.v index ec02a6854..7626eca81 100644 --- a/test_regress/t/t_pp_display.v +++ b/test_regress/t/t_pp_display.v @@ -1,4 +1,3 @@ -// $Id: t_delay.v 965 2007-10-31 20:29:07Z wsnyder $ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_pp_dupdef.pl b/test_regress/t/t_pp_dupdef.pl index 1ecdda807..c7bd0e11c 100755 --- a/test_regress/t/t_pp_dupdef.pl +++ b/test_regress/t/t_pp_dupdef.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_pp_dupdef.v b/test_regress/t/t_pp_dupdef.v index 8de2b8abe..19a3dd52d 100644 --- a/test_regress/t/t_pp_dupdef.v +++ b/test_regress/t/t_pp_dupdef.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -11,7 +10,7 @@ module t; `define DUPP paramed(x) (x) `define DUPP paramed(x,z) (x*z) - + initial $stop; // Should have failed endmodule diff --git a/test_regress/t/t_pp_dupdef_bad.pl b/test_regress/t/t_pp_dupdef_bad.pl index bae7876fa..3e13c3aa2 100755 --- a/test_regress/t/t_pp_dupdef_bad.pl +++ b/test_regress/t/t_pp_dupdef_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2008 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_pp_lib.pl b/test_regress/t/t_pp_lib.pl index 3af4cfb73..ba7a1ac3d 100755 --- a/test_regress/t/t_pp_lib.pl +++ b/test_regress/t/t_pp_lib.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_pp_lib.v b/test_regress/t/t_pp_lib.v index 4e3646910..5a5d7e4ac 100644 --- a/test_regress/t/t_pp_lib.v +++ b/test_regress/t/t_pp_lib.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_pp_lib_inc.v b/test_regress/t/t_pp_lib_inc.v index 50f55aade..4c32a16fe 100644 --- a/test_regress/t/t_pp_lib_inc.v +++ b/test_regress/t/t_pp_lib_inc.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_pp_lib_library.v b/test_regress/t/t_pp_lib_library.v index 4c231a010..1059eedcf 100644 --- a/test_regress/t/t_pp_lib_library.v +++ b/test_regress/t/t_pp_lib_library.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_pp_misdef_bad.pl b/test_regress/t/t_pp_misdef_bad.pl index dab274477..3b25498f0 100755 --- a/test_regress/t/t_pp_misdef_bad.pl +++ b/test_regress/t/t_pp_misdef_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can @@ -11,7 +10,7 @@ compile ( v_flags2 => ["--lint-only"], fails=>1, expect=> -'%Error: t/t_pp_misdef_bad.v:11: Define or directive not defined: `NOTDEF +'%Error: t/t_pp_misdef_bad.v:\d+: Define or directive not defined: `NOTDEF %Error: Exiting due to.*', ) if $Last_Self->{v3}; diff --git a/test_regress/t/t_pp_misdef_bad.v b/test_regress/t/t_pp_misdef_bad.v index 90474ae64..c1f00cf73 100644 --- a/test_regress/t/t_pp_misdef_bad.v +++ b/test_regress/t/t_pp_misdef_bad.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_pp_pragmas.pl b/test_regress/t/t_pp_pragmas.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_pp_pragmas.pl +++ b/test_regress/t/t_pp_pragmas.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_pp_pragmas.v b/test_regress/t/t_pp_pragmas.v index de597c51d..bdfaf21bc 100644 --- a/test_regress/t/t_pp_pragmas.v +++ b/test_regress/t/t_pp_pragmas.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_preproc.pl b/test_regress/t/t_preproc.pl index 94200d273..e72c8a9ff 100755 --- a/test_regress/t/t_preproc.pl +++ b/test_regress/t/t_preproc.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_preproc.v b/test_regress/t/t_preproc.v index cee0b2e03..afc6ab0d8 100644 --- a/test_regress/t/t_preproc.v +++ b/test_regress/t/t_preproc.v @@ -1,6 +1,6 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // +// // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2004-2007 by Wilson Snyder. diff --git a/test_regress/t/t_preproc_dos.pl b/test_regress/t/t_preproc_dos.pl index c5c172ab9..be30cdcea 100755 --- a/test_regress/t/t_preproc_dos.pl +++ b/test_regress/t/t_preproc_dos.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2006-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_preproc_ifdef.pl b/test_regress/t/t_preproc_ifdef.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_preproc_ifdef.pl +++ b/test_regress/t/t_preproc_ifdef.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_preproc_ifdef.v b/test_regress/t/t_preproc_ifdef.v index 61cfad07d..7c5e23be6 100644 --- a/test_regress/t/t_preproc_ifdef.v +++ b/test_regress/t/t_preproc_ifdef.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_preproc_kwd.pl b/test_regress/t/t_preproc_kwd.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_preproc_kwd.pl +++ b/test_regress/t/t_preproc_kwd.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v index e78ff9158..b50f36655 100644 --- a/test_regress/t/t_preproc_kwd.v +++ b/test_regress/t/t_preproc_kwd.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_preproc_psl.v b/test_regress/t/t_preproc_psl.v index 6dc24e117..c65b79682 100644 --- a/test_regress/t/t_preproc_psl.v +++ b/test_regress/t/t_preproc_psl.v @@ -1,6 +1,6 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // +// // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2005 by Wilson Snyder. diff --git a/test_regress/t/t_preproc_psl_off.pl b/test_regress/t/t_preproc_psl_off.pl index 04130bd67..8cf95784e 100755 --- a/test_regress/t/t_preproc_psl_off.pl +++ b/test_regress/t/t_preproc_psl_off.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_preproc_psl_on.pl b/test_regress/t/t_preproc_psl_on.pl index d4a69f60e..e139562ca 100755 --- a/test_regress/t/t_preproc_psl_on.pl +++ b/test_regress/t/t_preproc_psl_on.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_psl_basic.pl b/test_regress/t/t_psl_basic.pl index f4de78c1d..ba8e7db41 100755 --- a/test_regress/t/t_psl_basic.pl +++ b/test_regress/t/t_psl_basic.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_psl_basic.v b/test_regress/t/t_psl_basic.v index 11387ff22..8fe62c188 100644 --- a/test_regress/t/t_psl_basic.v +++ b/test_regress/t/t_psl_basic.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_psl_basic_cover.pl b/test_regress/t/t_psl_basic_cover.pl index 9aa2f2486..b82f967bb 100755 --- a/test_regress/t/t_psl_basic_cover.pl +++ b/test_regress/t/t_psl_basic_cover.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_psl_basic_off.pl b/test_regress/t/t_psl_basic_off.pl index 52cf266c8..dc7210677 100755 --- a/test_regress/t/t_psl_basic_off.pl +++ b/test_regress/t/t_psl_basic_off.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_select_bad_msb.pl b/test_regress/t/t_select_bad_msb.pl index 88f5d7df8..e9d565e4e 100755 --- a/test_regress/t/t_select_bad_msb.pl +++ b/test_regress/t/t_select_bad_msb.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_select_bad_msb.v b/test_regress/t/t_select_bad_msb.v index b52b9dfde..26198e9cf 100644 --- a/test_regress/t/t_select_bad_msb.v +++ b/test_regress/t/t_select_bad_msb.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_select_bad_range.pl b/test_regress/t/t_select_bad_range.pl index 34d7c1671..ce3675fed 100755 --- a/test_regress/t/t_select_bad_range.pl +++ b/test_regress/t/t_select_bad_range.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_select_bad_range.v b/test_regress/t/t_select_bad_range.v index af8478eb9..3f7cbb15e 100644 --- a/test_regress/t/t_select_bad_range.v +++ b/test_regress/t/t_select_bad_range.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_select_index.pl b/test_regress/t/t_select_index.pl index c8354c35b..13b6d7474 100755 --- a/test_regress/t/t_select_index.pl +++ b/test_regress/t/t_select_index.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_select_index.v b/test_regress/t/t_select_index.v index 480730117..53ab68565 100644 --- a/test_regress/t/t_select_index.v +++ b/test_regress/t/t_select_index.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_select_plus.pl b/test_regress/t/t_select_plus.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_select_plus.pl +++ b/test_regress/t/t_select_plus.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_select_plus.v b/test_regress/t/t_select_plus.v index caec81a87..09f4cfd12 100644 --- a/test_regress/t/t_select_plus.v +++ b/test_regress/t/t_select_plus.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -26,7 +25,7 @@ module t (/*AUTOARG*/ to[bitn +: 4] = cyc[3:0]; to[bitn -: 4] = cyc[3:0]; end - + always @ (posedge clk) begin //$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n",$time, cyc, nibblep, nibblem, from^to); cyc <= cyc + 8'd1; diff --git a/test_regress/t/t_select_plusloop.pl b/test_regress/t/t_select_plusloop.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_select_plusloop.pl +++ b/test_regress/t/t_select_plusloop.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_select_plusloop.v b/test_regress/t/t_select_plusloop.v index 1db5f1022..b15b01019 100644 --- a/test_regress/t/t_select_plusloop.v +++ b/test_regress/t/t_select_plusloop.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -44,12 +43,12 @@ module t (/*AUTOARG*/ // verilator lint_on WIDTH end else if (cyc==90) begin - wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6; + wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6; wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6; wide[82 +: 4] <=4'h6; end else if (cyc==91) begin - wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1; + wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1; wide[41] <=1'b1; quad[41] <=1'b1; wide[81] <=1'b1; end diff --git a/test_regress/t/t_select_runtime_range.pl b/test_regress/t/t_select_runtime_range.pl index c8354c35b..13b6d7474 100755 --- a/test_regress/t/t_select_runtime_range.pl +++ b/test_regress/t/t_select_runtime_range.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_select_runtime_range.v b/test_regress/t/t_select_runtime_range.v index 95c559412..af2a5dc16 100644 --- a/test_regress/t/t_select_runtime_range.v +++ b/test_regress/t/t_select_runtime_range.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_select_set.pl b/test_regress/t/t_select_set.pl index c8354c35b..13b6d7474 100755 --- a/test_regress/t/t_select_set.pl +++ b/test_regress/t/t_select_set.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_select_set.v b/test_regress/t/t_select_set.v index 74873d66e..ff6d97bc1 100644 --- a/test_regress/t/t_select_set.v +++ b/test_regress/t/t_select_set.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_sys_file.pl b/test_regress/t/t_sys_file.pl index 6b72957e6..8a3b1f1d3 100644 --- a/test_regress/t/t_sys_file.pl +++ b/test_regress/t/t_sys_file.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_file.v b/test_regress/t/t_sys_file.v index 935f7cb9c..8fdc2dca9 100644 --- a/test_regress/t/t_sys_file.v +++ b/test_regress/t/t_sys_file.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_sys_readmem.pl b/test_regress/t/t_sys_readmem.pl index 7bfdbe852..e2a0c97fa 100755 --- a/test_regress/t/t_sys_readmem.pl +++ b/test_regress/t/t_sys_readmem.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_readmem.v b/test_regress/t/t_sys_readmem.v index a237be134..ef1af005c 100644 --- a/test_regress/t/t_sys_readmem.v +++ b/test_regress/t/t_sys_readmem.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -55,7 +54,7 @@ module t; if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop; if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop; end - + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_sys_readmem_b.mem b/test_regress/t/t_sys_readmem_b.mem index e5ae5bf92..b883eb0fa 100644 --- a/test_regress/t/t_sys_readmem_b.mem +++ b/test_regress/t/t_sys_readmem_b.mem @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_readmem_b_8.mem b/test_regress/t/t_sys_readmem_b_8.mem index 8c6546ad5..db0ff6509 100644 --- a/test_regress/t/t_sys_readmem_b_8.mem +++ b/test_regress/t/t_sys_readmem_b_8.mem @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_readmem_bad_addr.mem b/test_regress/t/t_sys_readmem_bad_addr.mem index dcba90f53..529c4c540 100644 --- a/test_regress/t/t_sys_readmem_bad_addr.mem +++ b/test_regress/t/t_sys_readmem_bad_addr.mem @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_readmem_bad_addr.pl b/test_regress/t/t_sys_readmem_bad_addr.pl index 52bc12be9..32b21555b 100755 --- a/test_regress/t/t_sys_readmem_bad_addr.pl +++ b/test_regress/t/t_sys_readmem_bad_addr.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_readmem_bad_addr.v b/test_regress/t/t_sys_readmem_bad_addr.v index 3bde466f3..677f6d8b9 100644 --- a/test_regress/t/t_sys_readmem_bad_addr.v +++ b/test_regress/t/t_sys_readmem_bad_addr.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_sys_readmem_bad_digit.mem b/test_regress/t/t_sys_readmem_bad_digit.mem index 403a1a93e..7d5097528 100644 --- a/test_regress/t/t_sys_readmem_bad_digit.mem +++ b/test_regress/t/t_sys_readmem_bad_digit.mem @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_readmem_bad_digit.pl b/test_regress/t/t_sys_readmem_bad_digit.pl index 720c8d450..395b5d4e7 100755 --- a/test_regress/t/t_sys_readmem_bad_digit.pl +++ b/test_regress/t/t_sys_readmem_bad_digit.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_readmem_bad_digit.v b/test_regress/t/t_sys_readmem_bad_digit.v index f42197a69..d3442228e 100644 --- a/test_regress/t/t_sys_readmem_bad_digit.v +++ b/test_regress/t/t_sys_readmem_bad_digit.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_sys_readmem_bad_end.mem b/test_regress/t/t_sys_readmem_bad_end.mem index 2bc10cf77..d6b0cde5b 100644 --- a/test_regress/t/t_sys_readmem_bad_end.mem +++ b/test_regress/t/t_sys_readmem_bad_end.mem @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_readmem_bad_end.pl b/test_regress/t/t_sys_readmem_bad_end.pl index 2913e8fc5..e8eca03b2 100755 --- a/test_regress/t/t_sys_readmem_bad_end.pl +++ b/test_regress/t/t_sys_readmem_bad_end.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_readmem_bad_end.v b/test_regress/t/t_sys_readmem_bad_end.v index 25c7e847c..d6f3e4902 100644 --- a/test_regress/t/t_sys_readmem_bad_end.v +++ b/test_regress/t/t_sys_readmem_bad_end.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_sys_readmem_bad_notfound.pl b/test_regress/t/t_sys_readmem_bad_notfound.pl index 7ac9031d4..b9587b42f 100755 --- a/test_regress/t/t_sys_readmem_bad_notfound.pl +++ b/test_regress/t/t_sys_readmem_bad_notfound.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_sys_readmem_bad_notfound.v b/test_regress/t/t_sys_readmem_bad_notfound.v index 2337d6c8e..e2a60a920 100644 --- a/test_regress/t/t_sys_readmem_bad_notfound.v +++ b/test_regress/t/t_sys_readmem_bad_notfound.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_sys_readmem_h.mem b/test_regress/t/t_sys_readmem_h.mem index d533c565f..1ea3be421 100644 --- a/test_regress/t/t_sys_readmem_h.mem +++ b/test_regress/t/t_sys_readmem_h.mem @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_trace_ena.v b/test_regress/t/t_trace_ena.v index a1f5a2d22..d4c53c0b0 100644 --- a/test_regress/t/t_trace_ena.v +++ b/test_regress/t/t_trace_ena.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_trace_ena_cc.pl b/test_regress/t/t_trace_ena_cc.pl index db33b246a..107915758 100644 --- a/test_regress/t/t_trace_ena_cc.pl +++ b/test_regress/t/t_trace_ena_cc.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_trace_ena_sc.pl b/test_regress/t/t_trace_ena_sc.pl index 3af4a9a71..778e5cb5b 100755 --- a/test_regress/t/t_trace_ena_sc.pl +++ b/test_regress/t/t_trace_ena_sc.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_trace_ena_sp.pl b/test_regress/t/t_trace_ena_sp.pl index f3a5bd656..4157ee96c 100755 --- a/test_regress/t/t_trace_ena_sp.pl +++ b/test_regress/t/t_trace_ena_sp.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_trace_off_cc.pl b/test_regress/t/t_trace_off_cc.pl index 184c9abf5..cbb72d86c 100755 --- a/test_regress/t/t_trace_off_cc.pl +++ b/test_regress/t/t_trace_off_cc.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_trace_off_sc.pl b/test_regress/t/t_trace_off_sc.pl index 4b09ae116..192fe2460 100755 --- a/test_regress/t/t_trace_off_sc.pl +++ b/test_regress/t/t_trace_off_sc.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_trace_off_sp.pl b/test_regress/t/t_trace_off_sp.pl index f0a960bb0..015e8cfee 100755 --- a/test_regress/t/t_trace_off_sp.pl +++ b/test_regress/t/t_trace_off_sp.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_unopt_combo.pl b/test_regress/t/t_unopt_combo.pl index 80b42932e..98d979847 100755 --- a/test_regress/t/t_unopt_combo.pl +++ b/test_regress/t/t_unopt_combo.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_unopt_combo.v b/test_regress/t/t_unopt_combo.v index 56e90998c..f3494ded5 100644 --- a/test_regress/t/t_unopt_combo.v +++ b/test_regress/t/t_unopt_combo.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -67,7 +66,7 @@ module file (/*AUTOARG*/ // Inputs crc ); - + input [31:0] crc; `ifdef ISOLATE output reg [31:0] b /* verilator isolate_assignments*/; diff --git a/test_regress/t/t_unopt_combo_bad.pl b/test_regress/t/t_unopt_combo_bad.pl index ead03c03c..4ad933d37 100755 --- a/test_regress/t/t_unopt_combo_bad.pl +++ b/test_regress/t/t_unopt_combo_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_unopt_combo_isolate.pl b/test_regress/t/t_unopt_combo_isolate.pl index 4c5021b57..04fcdc467 100755 --- a/test_regress/t/t_unopt_combo_isolate.pl +++ b/test_regress/t/t_unopt_combo_isolate.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_unopt_converge.v b/test_regress/t/t_unopt_converge.v index ed827962f..fc2e23591 100644 --- a/test_regress/t/t_unopt_converge.v +++ b/test_regress/t/t_unopt_converge.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_unopt_converge_print_bad.pl b/test_regress/t/t_unopt_converge_print_bad.pl index e6aaba8f9..c5a094e25 100755 --- a/test_regress/t/t_unopt_converge_print_bad.pl +++ b/test_regress/t/t_unopt_converge_print_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_unopt_converge_run_bad.pl b/test_regress/t/t_unopt_converge_run_bad.pl index 477b101a9..e8aadba77 100755 --- a/test_regress/t/t_unopt_converge_run_bad.pl +++ b/test_regress/t/t_unopt_converge_run_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_unopt_converge_unopt_bad.pl b/test_regress/t/t_unopt_converge_unopt_bad.pl index 45f504971..254c7c6a9 100755 --- a/test_regress/t/t_unopt_converge_unopt_bad.pl +++ b/test_regress/t/t_unopt_converge_unopt_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_unroll_signed.pl b/test_regress/t/t_unroll_signed.pl index 7e6b144bc..e2a0c97fa 100755 --- a/test_regress/t/t_unroll_signed.pl +++ b/test_regress/t/t_unroll_signed.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Revision: 1.1 $$Date$$Author$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_unroll_signed.v b/test_regress/t/t_unroll_signed.v index 04ff3dd9c..d9a5ded6e 100644 --- a/test_regress/t/t_unroll_signed.v +++ b/test_regress/t/t_unroll_signed.v @@ -1,4 +1,3 @@ -// $Revision: 1.1 $$Date$$Author$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_var_bad_hide.pl b/test_regress/t/t_var_bad_hide.pl index d8d6b4d46..fe0f2f59c 100755 --- a/test_regress/t/t_var_bad_hide.pl +++ b/test_regress/t/t_var_bad_hide.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_bad_hide.v b/test_regress/t/t_var_bad_hide.v index 4566a0169..2ae49ad51 100644 --- a/test_regress/t/t_var_bad_hide.v +++ b/test_regress/t/t_var_bad_hide.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_var_bad_rsvd.pl b/test_regress/t/t_var_bad_rsvd.pl index 0e2951cae..97f0e6411 100755 --- a/test_regress/t/t_var_bad_rsvd.pl +++ b/test_regress/t/t_var_bad_rsvd.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_bad_rsvd.v b/test_regress/t/t_var_bad_rsvd.v index b85f0ad13..48492614b 100644 --- a/test_regress/t/t_var_bad_rsvd.v +++ b/test_regress/t/t_var_bad_rsvd.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_var_bad_sameas.pl b/test_regress/t/t_var_bad_sameas.pl index b0d9e72f0..acf30794c 100755 --- a/test_regress/t/t_var_bad_sameas.pl +++ b/test_regress/t/t_var_bad_sameas.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_bad_sameas.v b/test_regress/t/t_var_bad_sameas.v index 60f6ac1e9..d09fe4a66 100644 --- a/test_regress/t/t_var_bad_sameas.v +++ b/test_regress/t/t_var_bad_sameas.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_var_dotted.v b/test_regress/t/t_var_dotted.v index add04f157..b9119fce2 100644 --- a/test_regress/t/t_var_dotted.v +++ b/test_regress/t/t_var_dotted.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -8,7 +7,7 @@ module t (/*AUTOARG*/ // Inputs clk ); - + // verilator lint_off MULTIDRIVEN wire [31:0] outb0c0; diff --git a/test_regress/t/t_var_dotted_inl0.pl b/test_regress/t/t_var_dotted_inl0.pl index b20fbfeb5..9e65640b5 100755 --- a/test_regress/t/t_var_dotted_inl0.pl +++ b/test_regress/t/t_var_dotted_inl0.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_dotted_inl1.pl b/test_regress/t/t_var_dotted_inl1.pl index 9f38d3590..0314d4315 100755 --- a/test_regress/t/t_var_dotted_inl1.pl +++ b/test_regress/t/t_var_dotted_inl1.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_dotted_inl2.pl b/test_regress/t/t_var_dotted_inl2.pl index 221962036..94e849532 100755 --- a/test_regress/t/t_var_dotted_inl2.pl +++ b/test_regress/t/t_var_dotted_inl2.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_in_assign_bad.pl b/test_regress/t/t_var_in_assign_bad.pl index 0a2972f2d..e0ca73a8d 100755 --- a/test_regress/t/t_var_in_assign_bad.pl +++ b/test_regress/t/t_var_in_assign_bad.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2005 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_in_assign_bad.v b/test_regress/t/t_var_in_assign_bad.v index 28659543e..8c1d8a9c5 100644 --- a/test_regress/t/t_var_in_assign_bad.v +++ b/test_regress/t/t_var_in_assign_bad.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_var_init.pl b/test_regress/t/t_var_init.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_var_init.pl +++ b/test_regress/t/t_var_init.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_init.v b/test_regress/t/t_var_init.v index 5bcdc29c1..577516707 100644 --- a/test_regress/t/t_var_init.v +++ b/test_regress/t/t_var_init.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_var_life.pl b/test_regress/t/t_var_life.pl index b16833df9..eb2df365a 100755 --- a/test_regress/t/t_var_life.pl +++ b/test_regress/t/t_var_life.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_life.v b/test_regress/t/t_var_life.v index e468b88d6..2a4520de1 100644 --- a/test_regress/t/t_var_life.v +++ b/test_regress/t/t_var_life.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_var_local.pl b/test_regress/t/t_var_local.pl index 9a7e1014a..e2a0c97fa 100755 --- a/test_regress/t/t_var_local.pl +++ b/test_regress/t/t_var_local.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_local.v b/test_regress/t/t_var_local.v index d0bf2c53a..be98098b4 100644 --- a/test_regress/t/t_var_local.v +++ b/test_regress/t/t_var_local.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_var_outoforder.pl b/test_regress/t/t_var_outoforder.pl index eff491d7a..2b6dd79c0 100755 --- a/test_regress/t/t_var_outoforder.pl +++ b/test_regress/t/t_var_outoforder.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2004 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_outoforder.v b/test_regress/t/t_var_outoforder.v index 4d6d13649..752a2d718 100644 --- a/test_regress/t/t_var_outoforder.v +++ b/test_regress/t/t_var_outoforder.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_regress/t/t_var_pins_cc.pl b/test_regress/t/t_var_pins_cc.pl index d4abf965f..58f9c27f7 100755 --- a/test_regress/t/t_var_pins_cc.pl +++ b/test_regress/t/t_var_pins_cc.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_pins_sc32.pl b/test_regress/t/t_var_pins_sc32.pl index 56ad3c51d..4e2f2eb42 100755 --- a/test_regress/t/t_var_pins_sc32.pl +++ b/test_regress/t/t_var_pins_sc32.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_pins_sc64.pl b/test_regress/t/t_var_pins_sc64.pl index d7092a59b..2df376be0 100755 --- a/test_regress/t/t_var_pins_sc64.pl +++ b/test_regress/t/t_var_pins_sc64.pl @@ -1,6 +1,5 @@ #!/usr/bin/perl if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } -# $Id:$ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2003 by Wilson Snyder. This program is free software; you can diff --git a/test_regress/t/t_var_pinsizes.v b/test_regress/t/t_var_pinsizes.v index bd81b462d..dd0395f72 100644 --- a/test_regress/t/t_var_pinsizes.v +++ b/test_regress/t/t_var_pinsizes.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_sc/.cvsignore b/test_sc/.gitignore similarity index 100% rename from test_sc/.cvsignore rename to test_sc/.gitignore diff --git a/test_sc/Makefile b/test_sc/Makefile index de29fbcc0..38239d2ad 100644 --- a/test_sc/Makefile +++ b/test_sc/Makefile @@ -1,4 +1,3 @@ -# $Id$ */ #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside source directory @@ -48,7 +47,7 @@ preproc: compile: cd obj_dir ; $(MAKE) -j 3 -f ../Makefile_obj -run: +run: obj_dir/simx ###################################################################### diff --git a/test_sc/Makefile_obj b/test_sc/Makefile_obj index 852b74f41..2477c164e 100644 --- a/test_sc/Makefile_obj +++ b/test_sc/Makefile_obj @@ -1,4 +1,4 @@ -# $Id$ -*- Makefile -*- +# -*- Makefile -*- #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside object directory diff --git a/test_sp/.cvsignore b/test_sp/.gitignore similarity index 100% rename from test_sp/.cvsignore rename to test_sp/.gitignore diff --git a/test_sp/Makefile b/test_sp/Makefile index 77109cfd9..1a0fae296 100644 --- a/test_sp/Makefile +++ b/test_sp/Makefile @@ -1,4 +1,3 @@ -# $Id$ */ #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside source directory @@ -47,7 +46,7 @@ compile: compile_dbg: cd obj_dir ; $(MAKE) OPT=-g -j 3 -f ../Makefile_obj -run: +run: obj_dir/simx coverage: diff --git a/test_sp/Makefile_obj b/test_sp/Makefile_obj index 3cdff8fe3..a599c1d32 100644 --- a/test_sp/Makefile_obj +++ b/test_sp/Makefile_obj @@ -1,4 +1,4 @@ -# $Id$ -*- Makefile -*- +# -*- Makefile -*- #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside object directory diff --git a/test_sp/sc_main.cpp b/test_sp/sc_main.cpp index ce62b7ba6..f44557f96 100644 --- a/test_sp/sc_main.cpp +++ b/test_sp/sc_main.cpp @@ -1,4 +1,4 @@ -// $Id$ -*- SystemC -*- +// -*- SystemC -*- // DESCRIPTION: Verilator Example: Top level main for invoking SystemC model // // Copyright 2003-2008 by Wilson Snyder. This program is free software; you can @@ -114,7 +114,7 @@ int sc_main(int argc, char* argv[]) { // Start of Test cout <<("Test beginning...\n"); - + reset_l = 1; while (VL_TIME_Q() < 60 && !passed) { #if WAVES diff --git a/test_v/input.vc b/test_v/input.vc index c9b8aba5b..87fea5f1b 100644 --- a/test_v/input.vc +++ b/test_v/input.vc @@ -1,7 +1,5 @@ -+librescan +libext+.v ++librescan +libext+.v -y ../test_v +incdir+../test_v +incdir+../include - - \ No newline at end of file diff --git a/test_v/t.v b/test_v/t.v index 663249001..389cbf21a 100644 --- a/test_v/t.v +++ b/test_v/t.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t (/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk, fastclk, reset_l ); diff --git a/test_v/t_arith.v b/test_v/t_arith.v index cb005fbf5..55785dbd3 100644 --- a/test_v/t_arith.v +++ b/test_v/t_arith.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_arith(/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk ); diff --git a/test_v/t_case.v b/test_v/t_case.v index 8cc9a6e45..7b49a76f4 100644 --- a/test_v/t_case.v +++ b/test_v/t_case.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -8,7 +7,7 @@ module t_case(/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk ); diff --git a/test_v/t_chg.v b/test_v/t_chg.v index 5f907c6da..f901344ca 100644 --- a/test_v/t_chg.v +++ b/test_v/t_chg.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_chg (/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk, fastclk ); @@ -64,7 +63,7 @@ endmodule module t_chg_a (/*AUTOARG*/ // Outputs - a_p1, b_p1, c_p1, d_p1, + a_p1, b_p1, c_p1, d_p1, // Inputs a, b, c, d ); diff --git a/test_v/t_clk.v b/test_v/t_clk.v index 6df9e530f..4d886b51c 100644 --- a/test_v/t_clk.v +++ b/test_v/t_clk.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_clk (/*AUTOARG*/ // Outputs - passed, + passed, // Inputs fastclk, clk, reset_l ); @@ -83,7 +82,7 @@ module t_clk (/*AUTOARG*/ end end end - + reg [7:0] resetted; always @ (posedge clk or negedge reset_int_) begin //$write("CLK4 %x\n", reset_l); diff --git a/test_v/t_clk_flop.v b/test_v/t_clk_flop.v index e06885b44..62a2baede 100644 --- a/test_v/t_clk_flop.v +++ b/test_v/t_clk_flop.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -8,7 +7,7 @@ module t_clk_flop (/*AUTOARG*/ // Outputs - q, q2, + q, q2, // Inputs clk, clk2, a ); diff --git a/test_v/t_clk_two.v b/test_v/t_clk_two.v index cf975ab94..05578df52 100644 --- a/test_v/t_clk_two.v +++ b/test_v/t_clk_two.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_v/t_func.v b/test_v/t_func.v index 3a13bb7eb..fed069489 100644 --- a/test_v/t_func.v +++ b/test_v/t_func.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_func (/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk ); diff --git a/test_v/t_func_grey2bin.v b/test_v/t_func_grey2bin.v index efbe44a4c..c6117ad18 100644 --- a/test_v/t_func_grey2bin.v +++ b/test_v/t_func_grey2bin.v @@ -1,4 +1,4 @@ -// $Id:$ -*- Verilog -*- +// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -15,11 +15,11 @@ module t_func_grey2bin (/*AUTOARG*/ // Outputs - b, + b, // Inputs g ); - + // surefire lint_off STMFOR parameter SZ = 5; @@ -34,6 +34,6 @@ module t_func_grey2bin (/*AUTOARG*/ integer i; always @(/*AUTOSENSE*/g) for (i=0; i> i); // surefire lint_off_line LATASS + b[i] = ^(g >> i); // surefire lint_off_line LATASS endmodule diff --git a/test_v/t_initial.v b/test_v/t_initial.v index 52e7ef13b..51f4f21cb 100644 --- a/test_v/t_initial.v +++ b/test_v/t_initial.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_initial(/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk ); @@ -25,12 +24,12 @@ module t_initial(/*AUTOARG*/ if (!_ranit) begin _ranit <= 1; $write("[%0t] t_initial: Running\n",$time); - + // Test $time // surefire lint_off CWECBB if ($time<20) $write("time<20\n"); // surefire lint_on CWECBB - + // Test $write $write ("[%0t] %m: User loaded ", $time); $display ("%b", user_loaded_value); diff --git a/test_v/t_initial_inc.v b/test_v/t_initial_inc.v index a1b5fe372..9aad43c46 100644 --- a/test_v/t_initial_inc.v +++ b/test_v/t_initial_inc.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_v/t_inst.v b/test_v/t_inst.v index 8ef80a627..49fcc4d3e 100644 --- a/test_v/t_inst.v +++ b/test_v/t_inst.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_inst(/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk, fastclk ); @@ -27,7 +26,7 @@ module t_inst(/*AUTOARG*/ wire da,db,dc,dd,de; reg [7:0] wa,wb,wc,wd,we; wire [7:0] qa,qb,qc,qd,qe; - + wire [5:0] ra; wire [4:0] rb; wire [29:0] rc; diff --git a/test_v/t_inst_a.v b/test_v/t_inst_a.v index 989d4a8e4..03265fb2e 100644 --- a/test_v/t_inst_a.v +++ b/test_v/t_inst_a.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_inst_a (/*AUTOARG*/ // Outputs - o_w5, o_w5_d1r, o_w40, o_w104, + o_w5, o_w5_d1r, o_w40, o_w104, // Inputs clk, i_w5, i_w40, i_w104 ); diff --git a/test_v/t_inst_b.v b/test_v/t_inst_b.v index 3d88efae3..a1b56f94c 100644 --- a/test_v/t_inst_b.v +++ b/test_v/t_inst_b.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_inst_b (/*AUTOARG*/ // Outputs - o_seq_d1r, o_com, o2_com, + o_seq_d1r, o_com, o2_com, // Inputs clk, i_seq, i_com, i2_com, wide_for_trace, wide_for_trace_2 ); diff --git a/test_v/t_loop.v b/test_v/t_loop.v index 720d609bf..b043c343e 100644 --- a/test_v/t_loop.v +++ b/test_v/t_loop.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_loop (/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk ); diff --git a/test_v/t_mem.v b/test_v/t_mem.v index 281226188..84447acbd 100644 --- a/test_v/t_mem.v +++ b/test_v/t_mem.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_mem (/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk ); @@ -24,7 +23,7 @@ module t_mem (/*AUTOARG*/ reg [31:0] wrd0 [15:0]; wire [3:0] sel = 4'h3; wire [31:0] selout = wrd0[sel]; - + // Must take LSBs into account in bit extract widths. wire [15:14] sixt = 2'b10; // surefire lint_off_line ASWCBB wire [16:14] sixt2 = 3'b110; // surefire lint_off_line ASWCBB @@ -38,7 +37,7 @@ module t_mem (/*AUTOARG*/ reg [2:0] np2_guard [7:6] /*verilator public*/; integer i; - + always @ (posedge clk) begin if (_mode!=0) begin $write("[%0t] t_mem: Running\n", $time); diff --git a/test_v/t_netlist.v b/test_v/t_netlist.v index 1c0b6ab73..3496145e3 100644 --- a/test_v/t_netlist.v +++ b/test_v/t_netlist.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_netlist (/*AUTOARG*/ // Outputs - passed, + passed, // Inputs fastclk, also_fastclk ); diff --git a/test_v/t_param.v b/test_v/t_param.v index f2898a328..d7cbe1d8e 100644 --- a/test_v/t_param.v +++ b/test_v/t_param.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_param(/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk ); @@ -64,7 +63,7 @@ module t_param(/*AUTOARG*/ parameter THREE_2WIDE = 2'b11; parameter ALSO_THREE_WIDE = THREE_BITS_WIDE; parameter THREEPP_32_WIDE = 2*8*2+3; - parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide + parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide // Width propagation doesn't care about LHS vs RHS // But the width of a RHS/LHS on a upper node does affect lower nodes; @@ -131,7 +130,7 @@ module t_param(/*AUTOARG*/ // verilator lint_off WIDTH // surefire lint_off ASWCMB // surefire lint_off ASWCBB - eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop; + eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop; fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop; fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop; // verilator lint_on WIDTH diff --git a/test_v/t_param_a.v b/test_v/t_param_a.v index 2c13d4a64..ff3839a2a 100644 --- a/test_v/t_param_a.v +++ b/test_v/t_param_a.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -12,13 +11,13 @@ module t_param_a (/*AUTOARG*/ parameter X = 1; parameter FIVE = 0; // Overridden parameter TWO = 2; - + /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output [4:0] par; // From b of t_param_b.v output [X:0] varwidth; // From b of t_param_b.v // End of automatics - + t_param_b #(X,FIVE,TWO) b (/*AUTOINST*/ // Outputs .par (par[4:0]), diff --git a/test_v/t_param_b.v b/test_v/t_param_b.v index 5d493b674..904aaaddb 100644 --- a/test_v/t_param_b.v +++ b/test_v/t_param_b.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -12,7 +11,7 @@ module t_param_b (/*AUTOARG*/ parameter X = 1; parameter FIVE = 0; // Overridden parameter TWO = 2; - + output [4:0] par; output [X:0] varwidth; diff --git a/test_v/t_rnd.v b/test_v/t_rnd.v index 45b471359..9a54ec95d 100644 --- a/test_v/t_rnd.v +++ b/test_v/t_rnd.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_rnd(/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk ); diff --git a/test_v/t_task.v b/test_v/t_task.v index fa718cc2c..d8dc943b5 100644 --- a/test_v/t_task.v +++ b/test_v/t_task.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -6,7 +5,7 @@ module t_task (/*AUTOARG*/ // Outputs - passed, + passed, // Inputs clk ); diff --git a/test_v/top.v b/test_v/top.v index ee5ea0b7e..1166bf320 100644 --- a/test_v/top.v +++ b/test_v/top.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, @@ -8,7 +7,7 @@ module top (/*AUTOARG*/ // Outputs - passed, out_small, out_quad, out_wide, + passed, out_small, out_quad, out_wide, // Inputs clk, fastclk, reset_l, in_small, in_quad, in_wide ); @@ -17,7 +16,7 @@ module top (/*AUTOARG*/ input clk; input fastclk; input reset_l; - + output [1:0] out_small; output [39:0] out_quad; output [69:0] out_wide; diff --git a/test_vcs/.cvsignore b/test_vcs/.gitignore similarity index 100% rename from test_vcs/.cvsignore rename to test_vcs/.gitignore diff --git a/test_vcs/Makefile b/test_vcs/Makefile index e7088690c..aae18d749 100644 --- a/test_vcs/Makefile +++ b/test_vcs/Makefile @@ -1,4 +1,3 @@ -# $Id$ */ #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside source directory diff --git a/test_vcs/bench.v b/test_vcs/bench.v index 7ac3bc7f9..013901485 100644 --- a/test_vcs/bench.v +++ b/test_vcs/bench.v @@ -1,4 +1,3 @@ -// $Id:$ // DESCRIPTION: Verilator Test: Top level testbench for VCS or other fully Verilog compliant simulators // // This file ONLY is placed into the Public Domain, for any use, diff --git a/test_verilated/.cvsignore b/test_verilated/.gitignore similarity index 100% rename from test_verilated/.cvsignore rename to test_verilated/.gitignore diff --git a/test_verilated/Makefile b/test_verilated/Makefile index a53798b19..00562c303 100644 --- a/test_verilated/Makefile +++ b/test_verilated/Makefile @@ -1,4 +1,3 @@ -# $Id$ */ #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside source directory @@ -21,7 +20,7 @@ export VERILATOR_ROOT # Pick up PERL and other variable settings include $(VERILATOR_ROOT)/include/verilated.mk -VERILATOR_SW += +VERILATOR_SW += ifeq ($(VERILATOR_NO_DEBUG),) VERILATOR_SW += --debug endif diff --git a/test_verilated/Makefile_obj b/test_verilated/Makefile_obj index 4afdc6a60..b64650d74 100644 --- a/test_verilated/Makefile_obj +++ b/test_verilated/Makefile_obj @@ -1,4 +1,4 @@ -# $Id$ -*- Makefile -*- +# -*- Makefile -*- #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside object directory diff --git a/test_verilated/sim_main.cpp b/test_verilated/sim_main.cpp index b59653119..95c189221 100644 --- a/test_verilated/sim_main.cpp +++ b/test_verilated/sim_main.cpp @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator Test: Top level main for invoking model // // Copyright 2003-2008 by Wilson Snyder. This program is free software; you can diff --git a/test_verilated/sim_main.v b/test_verilated/sim_main.v index 1110086c5..23d0f4143 100644 --- a/test_verilated/sim_main.v +++ b/test_verilated/sim_main.v @@ -1,4 +1,3 @@ -// $Id$ // DESCRIPTION: Verilator Test: Top level main for invoking model // // Copyright 2003-2008 by Wilson Snyder. This program is free software; you can @@ -7,7 +6,7 @@ module sim_main; /*verilator public_module*/ - + reg clk; reg check; wire done; diff --git a/test_verilated/vgen.pl b/test_verilated/vgen.pl index 98994a30e..350b6f00f 100755 --- a/test_verilated/vgen.pl +++ b/test_verilated/vgen.pl @@ -1,5 +1,4 @@ #!/usr/bin/perl -w -#$Id$ ###################################################################### # # This program is Copyright 2001-2008 by Wilson Snyder. @@ -7,12 +6,12 @@ # This program is free software; you can redistribute it and/or modify # it under the terms of either the GNU General Public License or the # Perl Artistic License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# ###################################################################### require 5.006_001; @@ -38,7 +37,7 @@ use vars qw (@Blocks #====================================================================== -# width=> Number of bits the output size is, 0=you tell me. +# width=> Number of bits the output size is, 0=you tell me. # func=> What to put in output file # signed=> 0=unsigned output, 1=signed output, '%1'=signed if op1 signed # em=> How to calculate emulated return value @@ -227,7 +226,6 @@ write_output_v("vgen.v") if !$Opt_Sc; #---------------------------------------------------------------------- sub usage { - print '$Id$ ', "\n"; pod2usage(-verbose=>2, -exitval => 2); exit (1); } @@ -240,7 +238,7 @@ sub parameter { my $param = shift; die "%Error: Unknown parameter: $param\n"; } - + ####################################################################### ####################################################################### ####################################################################### @@ -389,7 +387,7 @@ sub rnd_int { return 1 if ($v<60); return rnd32(); } - + sub rnd { return (int(rand($_[0]))) if ($_[0] < (1<<15)); return (rnd32() % $_[0]); @@ -1019,7 +1017,7 @@ sub tree_dump { my $treeref = shift; print Dumper($treeref); } - + ####################################################################### __END__ @@ -1060,7 +1058,7 @@ down to a NOP. =item --numops -Number of operations to create. +Number of operations to create. =item --raise