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Fix grammar error exposed with Verilog-Perl rev 55458 ++ -- fix

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@1072 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2008-06-05 20:49:52 +00:00
parent bb038e86a2
commit 056f72f27f
1 changed files with 4 additions and 4 deletions
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8
src/verilog.y
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@ -660,8 +660,8 @@ genItemList: genItem { $$ = $1; }
genItem: modOrGenItem { $$ = $1; }
| yCASE '(' expr ')' genCaseListE yENDCASE { $$ = new AstGenCase($1,$3,$5); }
| yIF expr genItemBlock %prec prLOWER_THAN_ELSE { $$ = new AstGenIf($1,$2,$3,NULL); }
| yIF expr genItemBlock yELSE genItemBlock { $$ = new AstGenIf($1,$2,$3,$5); }
| yIF '(' expr ')' genItemBlock %prec prLOWER_THAN_ELSE { $$ = new AstGenIf($1,$3,$5,NULL); }
| yIF '(' expr ')' genItemBlock yELSE genItemBlock { $$ = new AstGenIf($1,$3,$5,$7); }
| yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' genItemBlock
{ $$ = new AstGenFor($1, new AstAssign($4,$3,$5)
,$7, new AstAssign($10,$9,$11)
@ -931,8 +931,8 @@ stmt: ';' { $$ = NULL; }
// Case/If
stateCaseForIf: caseStmt caseAttrE caseListE yENDCASE { $$ = $1; if ($3) $1->addItemsp($3); }
| yIF expr stmtBlock %prec prLOWER_THAN_ELSE { $$ = new AstIf($1,$2,$3,NULL); }
| yIF expr stmtBlock yELSE stmtBlock { $$ = new AstIf($1,$2,$3,$5); }
| yIF '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE { $$ = new AstIf($1,$3,$5,NULL); }
| yIF '(' expr ')' stmtBlock yELSE stmtBlock { $$ = new AstIf($1,$3,$5,$7); }
| yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' stmtBlock
{ $$ = new AstFor($1, new AstAssign($4,$3,$5)
,$7, new AstAssign($10,$9,$11)