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Tests: Rename interface-to-wire (#5649 test partial)

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This commit is contained in:
Wilson Snyder 2024-11-30 19:04:31 -05:00
parent 2284ada723
commit 5021989cb6
8 changed files with 12 additions and 10 deletions
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5
test_regress/t/t_iface_wire_bad.out
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@ -1,5 +0,0 @@
%Error: t/t_iface_wire_bad.v:16:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a__Viftop' is an interface.
: ... note: In instance 't'
16 | wire wbad = sub.a;
| ^
%Error: Exiting due to

5
test_regress/t/t_iface_wire_bad_param.out
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@ -1,5 +0,0 @@
%Error: Internal Error: t/t_iface_wire_bad_param.v:16:20: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ./V3Ast__gen_impl.h:#
: ... note: In instance 't'
16 | wire wbad = sub.a;
| ^
... See the manual at https://verilator.org/verilator_doc.html for more assistance.

5
test_regress/t/t_interface_wire_bad.out Normal file
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@ -0,0 +1,5 @@
%Error: t/t_interface_wire_bad.v:17:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a__Viftop' is an interface.
: ... note: In instance 't'
17 | wire wbad = sub.a;
| ^
%Error: Exiting due to

0
test_regress/t/t_iface_wire_bad.py → test_regress/t/t_interface_wire_bad.py
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1
test_regress/t/t_iface_wire_bad.v → test_regress/t/t_interface_wire_bad.v
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@ -13,5 +13,6 @@ endmodule
module t; module t;
Sub sub(); Sub sub();
// Issue #5649
wire wbad = sub.a; wire wbad = sub.a;
endmodule endmodule

5
test_regress/t/t_interface_wire_bad_param.out Normal file
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@ -0,0 +1,5 @@
%Error: Internal Error: t/t_interface_wire_bad_param.v:17:20: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ./V3Ast__gen_impl.h:#
: ... note: In instance 't'
17 | wire wbad = sub.a;
| ^
... See the manual at https://verilator.org/verilator_doc.html for more assistance.

0
test_regress/t/t_iface_wire_bad_param.py → test_regress/t/t_interface_wire_bad_param.py
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1
test_regress/t/t_iface_wire_bad_param.v → test_regress/t/t_interface_wire_bad_param.v
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@ -13,5 +13,6 @@ endmodule
module t; module t;
Sub #(0) sub(); Sub #(0) sub();
// Issue #5649
wire wbad = sub.a; wire wbad = sub.a;
endmodule endmodule