Tests: Interface-to-wire (#5649 test partial)

test_regress/t/t_iface_wire_bad.out

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+%Error: t/t_iface_wire_bad.v:16:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a__Viftop' is an interface.
+                                  : ... note: In instance 't'
+   16 |    wire wbad = sub.a;
+      |                    ^
+%Error: Exiting due to

test_regress/t/t_iface_wire_bad.py

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+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_iface_wire_bad.v

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+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface Ifc;
+endinterface
+
+module Sub;
+   Ifc a();
+endmodule
+
+module t;
+   Sub sub();
+   wire wbad = sub.a;
+endmodule

test_regress/t/t_iface_wire_bad_param.out

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+%Error: Internal Error: t/t_iface_wire_bad_param.v:16:20: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ./V3Ast__gen_impl.h:#
+                                                        : ... note: In instance 't'
+   16 |    wire wbad = sub.a;
+      |                    ^
+                        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

test_regress/t/t_iface_wire_bad_param.py

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+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_iface_wire_bad_param.v

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+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface Ifc;
+endinterface
+
+module Sub #(parameter P);
+   Ifc a();
+endmodule
+
+module t;
+   Sub #(0) sub();
+   wire wbad = sub.a;
+endmodule