Fix short-circuting on method calls (#5486).

Changes

@@ -64,6 +64,7 @@ Verilator 5.029 devel
 * Fix --binary with .cpp PLI filenames under relative directory paths.
 * Fix extra dot in coverage point hierarchy when using name()=''.
 * Fix short-circuting with associative array access (#5484). [Ethan Sifferman]
+* Fix short-circuting on method calls (#5486). [Ethan Sifferman]
 
 
 Verilator 5.028 2024-08-21

src/V3AstNodes.cpp

@@ -2896,6 +2896,15 @@ void AstCMethodHard::setPurity() {
     auto isPureIt = isPureMethod.find(name());
     UASSERT_OBJ(isPureIt != isPureMethod.end(), this, "Unknown purity of method " + name());
     m_pure = isPureIt->second;
+    if (!m_pure) return;
+    if (!fromp()->isPure()) m_pure = false;
+    if (!m_pure) return;
+    for (AstNodeExpr* argp = pinsp(); argp; argp = VN_AS(argp->nextp(), NodeExpr)) {
+        if (!argp->isPure()) {
+            m_pure = false;
+            return;
+        }
+    }
 }
 
 void AstCUse::dump(std::ostream& str) const {

test_regress/t/t_a7_hier_block_cmake.py

@@ -26,9 +26,11 @@ test.run(logfile=test.obj_dir + "/cmake.log",
              "-DCMAKE_PREFIX_PATH=" + os.environ["VERILATOR_ROOT"], threads
          ])
 
-test.run(
+test.run(logfile=test.obj_dir + "/build.log",
-    logfile=test.obj_dir + "/build.log",
+         cmd=[
-    cmd=['cd "' + test.obj_dir + '" && cmake --build', '.', '--', "CXX_FLAGS=" + str(threads)])
+             'cd "' + test.obj_dir + '" && cmake --build', '.', ('-v' if test.verbose else ''),
+             '--', "CXX_FLAGS=" + str(threads)
+         ])
 
 test.run(logfile=test.obj_dir + "/run.log",
          cmd=['cd "' + test.obj_dir + '" && ./t_hier_block_cmake', '.'])

test_regress/t/t_math_shortcircuit_dynsel.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_math_shortcircuit_dynsel.v

@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   logic [31:0] dict [int] [];
+   // verilator lint_off WIDTHTRUNC
+   function automatic logic f(int a);
+      int dict_size = dict.size;
+      logic next_exists = dict.next(a);
+      // incorrectly inserts element at `a`
+      logic next_nonzero = !next_exists || (dict[a].size != 0);
+      if (dict_size != dict.size) begin
+         $display("Assertion failed: dict_size mismatch");
+         $display("Initial size: %0d, New size: %0d", dict_size, dict.size);
+         $display("Dictionary contents:");
+         foreach (dict[key]) begin
+            $display(" Key: %0d, Value: %0d", key, dict[key]);
+         end
+         $error;
+      end
+      return next_nonzero;
+   endfunction
+   initial begin
+      logic r = f(0);
+      $display(r);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule