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33 lines
1.0 KiB
Systemverilog
33 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic [31:0] dict [int] [];
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// verilator lint_off WIDTHTRUNC
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function automatic logic f(int a);
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int dict_size = dict.size;
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logic next_exists = dict.next(a);
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// incorrectly inserts element at `a`
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logic next_nonzero = !next_exists || (dict[a].size != 0);
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if (dict_size != dict.size) begin
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$display("Assertion failed: dict_size mismatch");
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$display("Initial size: %0d, New size: %0d", dict_size, dict.size);
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$display("Dictionary contents:");
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foreach (dict[key]) begin
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$display(" Key: %0d, Value: %0d", key, dict[key]);
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end
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$error;
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end
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return next_nonzero;
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endfunction
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initial begin
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logic r = f(0);
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$display(r);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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