Fix short-circuting with associative array access (#5484).

Changes

@@ -63,6 +63,7 @@ Verilator 5.029 devel
 * Fix timing mode not exiting on empty events (#5472).
 * Fix --binary with .cpp PLI filenames under relative directory paths.
 * Fix extra dot in coverage point hierarchy when using name()=''.
+* Fix short-circuting with associative array access (#5484). [Ethan Sifferman]
 
 
 Verilator 5.028 2024-08-21

src/V3AstNodeExpr.h

@@ -4187,8 +4187,9 @@ public:
     bool cleanRhs() const override { return true; }
     bool sizeMattersLhs() const override { return false; }
     bool sizeMattersRhs() const override { return false; }
-    bool isGateOptimizable() const override { return true; }  // esp for V3Const::ifSameAssign
+    bool isGateOptimizable() const override { return false; }  // AssocSel creates on miss
     bool isPredictOptimizable() const override { return false; }
+    bool isPure() override { return false; }  // AssocSel creates on miss
     bool same(const AstNode* /*samep*/) const override { return true; }
     int instrCount() const override { return widthInstrs(); }
 };

test_regress/t/t_math_shortcircuit_assocsel.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_math_shortcircuit_assocsel.v

@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   logic [31:0] dict [int];
+   // verilator lint_off WIDTHTRUNC
+   function automatic logic f(int a);
+      int dict_size = dict.size;
+      logic next_exists = dict.next(a);
+      // incorrectly inserts element at `a`
+      logic next_nonzero = !next_exists || (dict[a] != 0);
+      if (dict_size != dict.size) begin
+         $display("Assertion failed: dict_size mismatch");
+         $display("Initial size: %0d, New size: %0d", dict_size, dict.size);
+         $display("Dictionary contents:");
+         foreach (dict[key]) begin
+            $display(" Key: %0d, Value: %0d", key, dict[key]);
+         end
+         $error;
+      end
+      return next_nonzero;
+   endfunction
+   initial begin
+      logic r = f(0);
+      $display(r);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule