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Fix parallel make running bison twice

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@1051 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2008-05-06 15:45:41 +00:00
parent f6c8888ee2
commit 36e84973ec
1 changed files with 5 additions and 2 deletions
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7
src/Makefile_obj.in
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@ -245,12 +245,15 @@ V3PreProc.o: V3PreProc.cpp V3PreLex.yy.cpp
#### Generated files
# Target rule called before parallel build to make generated files
serial:: V3Ast__gen_classes.h
serial:: V3Ast__gen_classes.h y.tab.c
V3Ast__gen_classes.h : $(ASTGEN) V3Ast.h V3AstNodes.h
$(PERL) $(ASTGEN) -I$(srcdir) --classes
y.tab.c y.tab.h: verilog.y $(HEADERS)
y.tab.h: y.tab.c
# Have only one output file in this rule to prevent parallel make issues
y.tab.c: verilog.y $(HEADERS)
@echo "If you get errors from verilog.y below, try upgrading bison to version 1.875 or newer."
${YACC} ${YFLAGS} $<
mv y.tab.c y_pregen.tab.c && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.c > y.tab.c