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Fix comma separated list of primitives. [by Bryan Brady]

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@1050 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2008-05-06 14:52:53 +00:00
parent f2bf6a037b
commit f6c8888ee2
3 changed files with 15 additions and 14 deletions
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2
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@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix parametrized defines calling define with comma. [Joshua Wise]
**** Fix comma separated list of primitives. [by Bryan Brady]
* Verilator 3.662 2008/04/25
*** Add Verilog 2005 $clog2() function.

16
src/verilog.y
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@ -1137,28 +1137,28 @@ gateDecl: yBUF delayE gateBufList ';' { $$ = $3; }
;
gateBufList: gateBuf { $$ = $1; }
| gateBuf ',' gateBuf { $$ = $1->addNext($3); }
| gateBufList ',' gateBuf { $$ = $1->addNext($3); }
;
gateNotList: gateNot { $$ = $1; }
| gateNot ',' gateNot { $$ = $1->addNext($3); }
| gateNotList ',' gateNot { $$ = $1->addNext($3); }
;
gateAndList: gateAnd { $$ = $1; }
| gateAnd ',' gateAnd { $$ = $1->addNext($3); }
| gateAndList ',' gateAnd { $$ = $1->addNext($3); }
;
gateNandList: gateNand { $$ = $1; }
| gateNand ',' gateNand { $$ = $1->addNext($3); }
| gateNandList ',' gateNand { $$ = $1->addNext($3); }
;
gateOrList: gateOr { $$ = $1; }
| gateOr ',' gateOr { $$ = $1->addNext($3); }
| gateOrList ',' gateOr { $$ = $1->addNext($3); }
;
gateNorList: gateNor { $$ = $1; }
| gateNor ',' gateNor { $$ = $1->addNext($3); }
| gateNorList ',' gateNor { $$ = $1->addNext($3); }
;
gateXorList: gateXor { $$ = $1; }
| gateXor ',' gateXor { $$ = $1->addNext($3); }
| gateXorList ',' gateXor { $$ = $1->addNext($3); }
;
gateXnorList: gateXnor { $$ = $1; }
| gateXnor ',' gateXnor { $$ = $1->addNext($3); }
| gateXnorList ',' gateXnor { $$ = $1->addNext($3); }
;
gateBuf: gateIdE instRangeE '(' varRefDotBit ',' expr ')' { $$ = new AstAssignW ($3,$4,$6); $$->allowImplicit(true); }

11
test_regress/t/t_gate_basic.v
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@ -15,8 +15,9 @@ module t (/*AUTOARG*/
reg [31:0] a;
reg [31:0] b;
wire [1:0] bf; buf BF0 (bf[0], a[0]),
BF1 (bf[1], a[1]);
wire [2:0] bf; buf BF0 (bf[0], a[0]),
BF1 (bf[1], a[1]),
BF2 (bf[2], a[2]);
// verilator lint_off IMPLICIT
not NT0 (nt0, a[0]);
@ -60,8 +61,7 @@ module t (/*AUTOARG*/
if (cyc==2) begin
a <= 32'h529ab56f;
b <= 32'h7835a237;
if (bf[0] !== 1'b0) $stop;
if (bf[1] !== 1'b0) $stop;
if (bf !== 3'b100) $stop;
if (nt0 !== 1'b1) $stop;
if (an0 !== 1'b0) $stop;
if (nd0 !== 1'b1) $stop;
@ -72,8 +72,7 @@ module t (/*AUTOARG*/
if (ba != 32'h18f6b034) $stop;
end
if (cyc==3) begin
if (bf[0] !== 1'b1) $stop;
if (bf[1] !== 1'b1) $stop;
if (bf !== 3'b111) $stop;
if (nt0 !== 1'b0) $stop;
if (an0 !== 1'b1) $stop;
if (nd0 !== 1'b0) $stop;