forked from github/verilator
29 lines
500 B
Verilog
29 lines
500 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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`begin_keywords "VAMS-2.3"
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module t (/*autoarg*/
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// Outputs
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aout,
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// Inputs
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in
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);
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input [15:0] in;
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output aout;
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wreal aout;
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parameter real lsb = 1;
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// verilator lint_off WIDTH
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assign aout = $itor(in) * lsb;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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