forked from github/verilator
Fix parameter real conversion from integer.
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Changes
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Changes
@ -13,6 +13,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix interface ports with comma lists, msg1058. [Ed Lander]
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**** Fix parameter real conversion from integer.
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**** Fix clang warnings, bug668. [Yutetsu Takatsukasa]
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@ -915,6 +915,9 @@ private:
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if (!nodep->valuep()->castInitArray()) { // No dtype at present, perhaps TODO
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widthCheck(nodep,"Initial value",nodep->valuep(),nodep->width(),nodep->widthMin());
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}
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if (nodep->isDouble() && !nodep->valuep()->isDouble()) {
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spliceCvtD(nodep->valuep());
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}
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}
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UINFO(4,"varWidthed "<<nodep<<endl);
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//if (debug()) nodep->dumpTree(cout," InitOut: ");
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18
test_regress/t/t_vams_wreal.pl
Executable file
18
test_regress/t/t_vams_wreal.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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28
test_regress/t/t_vams_wreal.v
Normal file
28
test_regress/t/t_vams_wreal.v
Normal file
@ -0,0 +1,28 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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`begin_keywords "VAMS-2.3"
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module t (/*autoarg*/
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// Outputs
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aout,
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// Inputs
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in
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);
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input [15:0] in;
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output aout;
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wreal aout;
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parameter real lsb = 1;
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// verilator lint_off WIDTH
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assign aout = $itor(in) * lsb;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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