forked from github/verilator
39 lines
777 B
Verilog
39 lines
777 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// IEEE 1800-2009 requires that any local definitions take precedence over
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// definitions in wildcard imported packages (section 26.3). Thus the code
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// below is valid SystemVerilog.
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//
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// This file ONLY is placed into the Public Domain, for any use, without
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// warranty, 2013 by Jie Xu
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package defs;
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parameter NUMBER = 8;
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localparam NUM = NUMBER;
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endpackage
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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import defs::*;
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// This also fails if we use localparam
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parameter NUM = 32;
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// Check we have the right definition
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always @(posedge clk) begin
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if (NUM == 32) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$stop;
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end
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end
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endmodule
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