forked from github/verilator
Fix package import preventing local var, bug599.
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@ -17,6 +17,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix package import of package imports, partial bug592. [Jeremy Bennett]
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**** Fix package import preventing local var, bug599. [Jeremy Bennett]
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* Verilator 3.843 2012/12/01
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@ -153,6 +153,8 @@ public:
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// Not found, will add in a moment.
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} else if (nodep==fnodep) { // Already inserted.
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// Good.
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} else if (foundp->imported()) { // From package
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// We don't throw VARHIDDEN as if the import is later the symbol table's import wouldn't warn
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} else if (nodep->castBegin() && fnodep->castBegin()
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&& nodep->castBegin()->generate()) {
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// Begin: ... blocks often replicate under genif/genfor, so simply suppress duplicate checks
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@ -262,7 +264,7 @@ public:
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symp->fallbackp(abovep);
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nodep->user1p(symp);
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checkDuplicate(abovep, nodep, name);
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abovep->insert(name, symp);
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abovep->reinsert(name, symp);
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return symp;
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}
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static bool existsModScope(AstNodeModule* nodep) {
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@ -669,7 +671,8 @@ private:
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} else if (findvarp != nodep) {
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UINFO(4,"DupVar: "<<nodep<<" ;; "<<foundp->nodep()<<endl);
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UINFO(4," found cur=se"<<(void*)m_curSymp<<" ;; parent=se"<<(void*)foundp->parentp()<<endl);
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if (foundp && foundp->parentp() == m_curSymp) { // Only when on same level
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if (foundp && foundp->parentp() == m_curSymp // Only when on same level
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&& !foundp->imported()) { // and not from package
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if ((findvarp->isIO() && nodep->isSignal())
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|| (findvarp->isSignal() && nodep->isIO())) {
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findvarp->combineType(nodep);
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@ -732,7 +735,8 @@ private:
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ins=true;
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} else if (findvarp != nodep) {
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UINFO(4,"DupVar: "<<nodep<<" ;; "<<foundp<<endl);
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if (foundp && foundp->parentp() == m_curSymp) { // Only when on same level
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if (foundp && foundp->parentp() == m_curSymp // Only when on same level
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&& !foundp->imported()) { // and not from package
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nodep->v3error("Duplicate declaration of enum value: "<<nodep->prettyName()<<endl
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<<findvarp->warnMore()<<"... Location of original declaration");
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} else {
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@ -759,7 +763,7 @@ private:
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}
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}
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m_curSymp->import(m_statep->symsp(), srcp, nodep->name());
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UINFO(2," Link Done: "<<nodep<<endl);
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UINFO(9," Link Done: "<<nodep<<endl);
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// No longer needed, but can't delete until any multi-instantiated modules are expanded
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}
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@ -152,6 +152,20 @@ public:
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if (m_fallbackp) return m_fallbackp->findIdFallback(name);
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return NULL;
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}
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private:
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bool importOneSymbol(VSymGraph* graphp, const string& name, const VSymEnt* srcp) {
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if (srcp->exported()
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&& !findIdFlat(name)) { // Don't insert over existing entry
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VSymEnt* symp = new VSymEnt(graphp, srcp);
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symp->exported(false); // Can't reimport an import without an export
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symp->imported(true);
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reinsert(name, symp);
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return true;
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} else {
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return false;
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}
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}
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public:
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bool import(VSymGraph* graphp, const VSymEnt* srcp, const string& id_or_star) {
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// Import tokens from source symbol table into this symbol table
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// Returns true if successful
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@ -159,21 +173,12 @@ public:
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if (id_or_star != "*") {
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IdNameMap::const_iterator it = srcp->m_idNameMap.find(id_or_star);
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if (it != m_idNameMap.end()) {
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if (it->second->exported()) {
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VSymEnt* symp = new VSymEnt(graphp, it->second);
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symp->exported(false); // Can't reimport an import without an export
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reinsert(it->first, symp);
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}
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importOneSymbol(graphp, it->first, it->second);
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}
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any = true; // Legal, though perhaps lint questionable to import nothing
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} else {
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for (IdNameMap::const_iterator it=srcp->m_idNameMap.begin(); it!=srcp->m_idNameMap.end(); ++it) {
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if (it->second->exported()) {
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VSymEnt* symp = new VSymEnt(graphp, it->second);
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symp->exported(false); // Can't reimport an import without an export
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reinsert(it->first, symp);
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any = true;
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}
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if (importOneSymbol(graphp, it->first, it->second)) any = true;
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}
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}
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return any;
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18
test_regress/t/t_package_param.pl
Executable file
18
test_regress/t/t_package_param.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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38
test_regress/t/t_package_param.v
Normal file
38
test_regress/t/t_package_param.v
Normal file
@ -0,0 +1,38 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// IEEE 1800-2009 requires that any local definitions take precedence over
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// definitions in wildcard imported packages (section 26.3). Thus the code
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// below is valid SystemVerilog.
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//
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// This file ONLY is placed into the Public Domain, for any use, without
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// warranty, 2013 by Jie Xu
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package defs;
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parameter NUMBER = 8;
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localparam NUM = NUMBER;
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endpackage
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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import defs::*;
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// This also fails if we use localparam
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parameter NUM = 32;
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// Check we have the right definition
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always @(posedge clk) begin
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if (NUM == 32) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$stop;
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end
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end
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endmodule
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