Support set_time_unit/set_time_precision in C traces, msg2261.

This commit is contained in:
Wilson Snyder 2017-06-20 19:33:58 -04:00
parent c7a5ff5e82
commit 6c87724af8
7 changed files with 1072 additions and 2 deletions

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@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
* Verilator 3.905 devel
*** Support set_time_unit/set_time_precision in C traces, msg2261.
*** Fix extract of packed array with non-zero LSB, bug1172. [James Pallister]
*** Fix shifts by more than 32-bit numbers, bug1174. [Clifford Wolf]

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@ -428,6 +428,15 @@ public:
void dump (double timestamp) { dump((vluint64_t)timestamp); }
void dump (vluint32_t timestamp) { dump((vluint64_t)timestamp); }
void dump (int timestamp) { dump((vluint64_t)timestamp); }
/// Set time units (s/ms, defaults to ns)
/// See also VL_TIME_PRECISION, and VL_TIME_MULTIPLIER in verilated.h
void set_time_unit (const char* unit) { m_sptrace.set_time_unit(unit); }
void set_time_unit (const string& unit) { set_time_unit(unit.c_str()); }
/// Set time resolution (s/ms, defaults to ns)
/// See also VL_TIME_PRECISION, and VL_TIME_MULTIPLIER in verilated.h
void set_time_resolution (const char* unit) { m_sptrace.set_time_resolution(unit); }
void set_time_resolution (const string& unit) { set_time_resolution(unit.c_str()); }
/// Internal class access
inline VerilatedVcd* spTrace () { return &m_sptrace; };
};

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@ -1463,9 +1463,12 @@ sub vcd_identical {
if (!-r $fn2) { $self->error("File does not exist $fn2\n"); return 0; }
{
# vcddiff to check transitions, if installed
my $out = `vcddiff --help`;
my $cmd = qq{vcddiff --help};
print "\t$cmd\n" if $::Debug;
my $out = `$cmd`;
if ($out !~ /Usage:/) { $self->skip("No vcddiff installed\n"); return 0; }
my $cmd = qq{vcddiff "$fn1" "$fn2"};
$cmd = qq{vcddiff "$fn1" "$fn2"};
print "\t$cmd\n" if $::Debug;
$out = `$cmd`;
if ($out ne '') {

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@ -0,0 +1,48 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
#include <verilated.h>
#include <verilated_vcd_c.h>
#if defined(T_TRACE_TIMESCALE)
# include "Vt_trace_timescale.h"
#else
# error "Unknown test"
#endif
unsigned long long main_time = 0;
double sc_time_stamp() {
return ((double)main_time) / VL_TIME_MULTIPLIER;
}
int main(int argc, char **argv, char **env) {
VM_PREFIX* top = new VM_PREFIX("top");
Verilated::debug(0);
Verilated::traceEverOn(true);
VerilatedVcdC* tfp = new VerilatedVcdC;
tfp->set_time_resolution("1ps");
tfp->set_time_unit("1ns");
top->trace(tfp,99);
tfp->open("obj_dir/t_trace_timescale/t_trace_timescale.vcd");
top->clk = 0;
while (main_time < 190*VL_TIME_MULTIPLIER) {
top->clk = ~top->clk;
top->eval();
tfp->dump((unsigned int)(main_time));
main_time += VL_TIME_MULTIPLIER/2;
}
tfp->close();
top->final();
printf ("*-* All Finished *-*\n");
return 0;
}

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@ -0,0 +1,965 @@
$version Generated by VerilatedVcd $end
$date Tue Jun 20 19:31:48 2017
$end
$timescale 1ps $end
$scope module top $end
$var wire 1 $ clk $end
$scope module t $end
$var wire 1 $ clk $end
$var wire 32 # cyc [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
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@ -0,0 +1,27 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
$Self->{vlt} or $Self->skip("Verilator only test");
compile (
make_top_shell => 0,
make_main => 0,
v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_timescale.cpp"],
make_flags => 'CPPFLAGS_ADD=-DVL_TIME_MULTIPLIER=1000',
);
execute (
check_finished=>1,
);
vcd_identical ("$Self->{obj_dir}/$Self->{name}.vcd",
"t/$Self->{name}.out");
ok(1);
1;

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@ -0,0 +1,16 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
module t
(
input wire clk
);
integer cyc; initial cyc = 0;
always @ (posedge clk) begin
cyc <= cyc + 1;
end
endmodule