forked from github/verilator
Tests: Fix broken vgen test, commentary.
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@ -2749,6 +2749,8 @@ private:
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AstNodeDType* expDTypep = m_vup->dtypeOverridep(nodep->dtypep());
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AstNodeDType* subDTypep = expDTypep;
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nodep->dtypeFrom(expDTypep);
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// We don't use LHS && RHS -- unspecified language corner, see t_math_signed5 test
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//bool expSigned = (nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned());
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if (AstNodeBiop* newp=replaceWithUOrSVersion(nodep, expDTypep->isSigned())) { VL_DANGLING(nodep);
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nodep = newp; // Process new node instead
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}
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@ -83,6 +83,7 @@
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w4_u = ((5'b01010 == (5'sb11111 / 5'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero
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`ifdef VCS // I-2014.03
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`checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate
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// Somewhat questionable, as spec says division signed depends on only LHS and RHS, however differs from others
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`else
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`checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ...
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`endif
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@ -82,8 +82,9 @@ our $Raise_Weight_Max = 50;
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'VADD'=> {weight=>1&&10, width=>0, sc=>1, terminal=>0, v=>'(%1 + %2)', },
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'VSUB'=> {weight=>1&&10, width=>0, sc=>1, terminal=>0, v=>'(%1 - %2)', },
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'VMUL'=> {weight=>1&&15,width=>0, sc=>1, terminal=>0, v=>'(%1 * %2)', }, # High % as rarely applyable
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'VDIV'=> {weight=>1&&8, width=>0, sc=>1, terminal=>0, v=>'((%2)==%xw\'h0 ? %xw\'%xsh0:(%1 / %2))', },
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'VMODDIV'=> {weight=>1&&8, width=>0, sc=>1, terminal=>0, v=>'((%2)==%xw\'h0 ? %xw\'%xsh0:(%1 %% %2))', },
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# Unspecified behavior with == (a-signed / b) -- see t_math_signed5.v test
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'VDIV'=> {weight=>1&&8, width=>0, signed=>0, sc=>1, terminal=>0, v=>'((%2)==%xw\'h0 ? %xw\'%xsh0:(%1 / %2))', },
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'VMODDIV'=> {weight=>1&&8, width=>0, signed=>0, sc=>1, terminal=>0, v=>'((%2)==%xw\'h0 ? %xw\'%xsh0:(%1 %% %2))', },
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#'VPOW'=> {weight=>2&&0,width=>-64, sc=>0, terminal=>0, v=>'(%1 ** %2)', },
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'VSHIFTL'=> {weight=>1&&8, width=>0, signed=>0, sc=>0, terminal=>0, v=>'(%1 << %2)', },
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'VSHIFTLS'=> {weight=>1&&8, width=>0, signed=>1, sc=>0, terminal=>0, v=>'(%1 <<< %2)', },
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