From 6c87724af8f33b36a62a564a2f683a99959efebb Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 20 Jun 2017 19:33:58 -0400 Subject: [PATCH] Support set_time_unit/set_time_precision in C traces, msg2261. --- Changes | 2 + include/verilated_vcd_c.h | 9 + test_regress/driver.pl | 7 +- test_regress/t/t_trace_timescale.cpp | 48 ++ test_regress/t/t_trace_timescale.out | 965 +++++++++++++++++++++++++++ test_regress/t/t_trace_timescale.pl | 27 + test_regress/t/t_trace_timescale.v | 16 + 7 files changed, 1072 insertions(+), 2 deletions(-) create mode 100644 test_regress/t/t_trace_timescale.cpp create mode 100644 test_regress/t/t_trace_timescale.out create mode 100755 test_regress/t/t_trace_timescale.pl create mode 100644 test_regress/t/t_trace_timescale.v diff --git a/Changes b/Changes index efeb53902..7658567df 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 3.905 devel +*** Support set_time_unit/set_time_precision in C traces, msg2261. + *** Fix extract of packed array with non-zero LSB, bug1172. [James Pallister] *** Fix shifts by more than 32-bit numbers, bug1174. [Clifford Wolf] diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index b84718b91..5f925e7d2 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -428,6 +428,15 @@ public: void dump (double timestamp) { dump((vluint64_t)timestamp); } void dump (vluint32_t timestamp) { dump((vluint64_t)timestamp); } void dump (int timestamp) { dump((vluint64_t)timestamp); } + /// Set time units (s/ms, defaults to ns) + /// See also VL_TIME_PRECISION, and VL_TIME_MULTIPLIER in verilated.h + void set_time_unit (const char* unit) { m_sptrace.set_time_unit(unit); } + void set_time_unit (const string& unit) { set_time_unit(unit.c_str()); } + /// Set time resolution (s/ms, defaults to ns) + /// See also VL_TIME_PRECISION, and VL_TIME_MULTIPLIER in verilated.h + void set_time_resolution (const char* unit) { m_sptrace.set_time_resolution(unit); } + void set_time_resolution (const string& unit) { set_time_resolution(unit.c_str()); } + /// Internal class access inline VerilatedVcd* spTrace () { return &m_sptrace; }; }; diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 350a7518a..454a6e6f7 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -1463,9 +1463,12 @@ sub vcd_identical { if (!-r $fn2) { $self->error("File does not exist $fn2\n"); return 0; } { # vcddiff to check transitions, if installed - my $out = `vcddiff --help`; + my $cmd = qq{vcddiff --help}; + print "\t$cmd\n" if $::Debug; + my $out = `$cmd`; if ($out !~ /Usage:/) { $self->skip("No vcddiff installed\n"); return 0; } - my $cmd = qq{vcddiff "$fn1" "$fn2"}; + + $cmd = qq{vcddiff "$fn1" "$fn2"}; print "\t$cmd\n" if $::Debug; $out = `$cmd`; if ($out ne '') { diff --git a/test_regress/t/t_trace_timescale.cpp b/test_regress/t/t_trace_timescale.cpp new file mode 100644 index 000000000..847b5b9df --- /dev/null +++ b/test_regress/t/t_trace_timescale.cpp @@ -0,0 +1,48 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +#include +#include + +#if defined(T_TRACE_TIMESCALE) +# include "Vt_trace_timescale.h" +#else +# error "Unknown test" +#endif + +unsigned long long main_time = 0; +double sc_time_stamp() { + return ((double)main_time) / VL_TIME_MULTIPLIER; +} + +int main(int argc, char **argv, char **env) { + VM_PREFIX* top = new VM_PREFIX("top"); + + Verilated::debug(0); + Verilated::traceEverOn(true); + + VerilatedVcdC* tfp = new VerilatedVcdC; + tfp->set_time_resolution("1ps"); + tfp->set_time_unit("1ns"); + + top->trace(tfp,99); + + tfp->open("obj_dir/t_trace_timescale/t_trace_timescale.vcd"); + + top->clk = 0; + + while (main_time < 190*VL_TIME_MULTIPLIER) { + top->clk = ~top->clk; + top->eval(); + tfp->dump((unsigned int)(main_time)); + main_time += VL_TIME_MULTIPLIER/2; + } + tfp->close(); + top->final(); + printf ("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_timescale.out b/test_regress/t/t_trace_timescale.out new file mode 100644 index 000000000..20a9ddce4 --- /dev/null +++ b/test_regress/t/t_trace_timescale.out @@ -0,0 +1,965 @@ +$version Generated by VerilatedVcd $end +$date Tue Jun 20 19:31:48 2017 + $end +$timescale 1ps $end + + $scope module top $end + $var wire 1 $ clk $end + $scope module t $end + $var wire 1 $ clk $end + $var wire 32 # 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This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} or $Self->skip("Verilator only test"); + +compile ( + make_top_shell => 0, + make_main => 0, + v_flags2 => ["--trace --exe $Self->{t_dir}/t_trace_timescale.cpp"], + make_flags => 'CPPFLAGS_ADD=-DVL_TIME_MULTIPLIER=1000', + ); + +execute ( + check_finished=>1, + ); + +vcd_identical ("$Self->{obj_dir}/$Self->{name}.vcd", + "t/$Self->{name}.out"); + +ok(1); +1; diff --git a/test_regress/t/t_trace_timescale.v b/test_regress/t/t_trace_timescale.v new file mode 100644 index 000000000..f9c6d1f21 --- /dev/null +++ b/test_regress/t/t_trace_timescale.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t + ( + input wire clk + ); + + integer cyc; initial cyc = 0; + + always @ (posedge clk) begin + cyc <= cyc + 1; + end +endmodule