forked from github/verilator
parent
31079ca8b5
commit
62387a0e32
2
Changes
2
Changes
@ -24,7 +24,7 @@ Verilator 4.215 devel
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* Fix nested generate if genblk naming (#3189). [yanx21]
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* Fix hang on recursive definition error (#3199). [Jonathan Kimmitt]
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* Fix display of signed without format (#3204). [Julie Schwartz]
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* Fix display of empty string constant (#3207). [Julie Schwartz]
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* Fix display of empty string constant (#3207) (#3215). [Julie Schwartz]
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* Fix incorrect width after and-or optimization (#3208). [Julie Schwartz]
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* Fix $fopen etc on integer arrays (#3214). [adrienlemasle]
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* Fix $size on dynamic strings (#3216).
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@ -1939,7 +1939,15 @@ private:
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} else {
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issigned = bdtypep->isSigned();
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}
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if (nodep->valuep()->dtypep()->widthSized()) {
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if (valueBdtypep->isString()) {
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// parameter X = "str", per IEEE is a number, not a string
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if (const auto* const constp = VN_CAST(nodep->valuep(), Const)) {
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if (constp->num().isString()) {
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width = constp->num().toString().length() * 8;
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}
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}
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if (width < 8) width = 8;
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} else if (nodep->valuep()->dtypep()->widthSized()) {
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width = nodep->valuep()->width();
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} else {
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if (nodep->valuep()->width() > 32) {
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@ -10,6 +10,11 @@ module t;
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parameter string OS = "O";
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parameter OI = "O"; // B is an integer of width 8
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parameter bit [31:0] NEST = "NEST";
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parameter bit [31:0] TEST = "TEST";
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bit [31:0] rest;
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string s;
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initial begin
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$display(">< == >%s<", "");
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$display(">< == >%s<", ES);
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@ -18,9 +23,23 @@ module t;
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if ($bits("") != 0) $stop;
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if ($bits("A") != 8) $stop;
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if ($bits(ES) != 0) $stop;
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if ($bits(EI) != 8) $stop;
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if ($bits(OS) != 8) $stop;
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if ($bits(OI) != 8) $stop;
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if (ES == "TEST") $stop; // Illegal in some simulators as not both strings
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if (EI == "TEST") $stop;
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if (OS == "TEST") $stop; // Illegal in some simulators as not both strings
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// verilator lint_off WIDTH
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if (OI == "TEST") $stop;
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if (rest == "TEST") $stop;
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if (ES == TEST) $stop;
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if (EI == TEST) $stop;
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if (OS == TEST) $stop;
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if (OI == TEST) $stop;
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if (rest == TEST) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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