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Fix parsing #1_2 delays

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This commit is contained in:
Wilson Snyder 2023-03-15 21:22:28 -04:00
parent 45690faea7
commit 36da6a3563
2 changed files with 11 additions and 1 deletions
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5
src/verilog.l
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@ -913,7 +913,10 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* "# 1'b0" is a delay value so must lex as "#" "1" "'b0" */
if (PARSEP->lexPrevToken()=='#') {
int shortlen = 0;
while (std::isdigit(yytext[shortlen])) ++shortlen;
if (std::isdigit(yytext[shortlen])) {
while (std::isdigit(yytext[shortlen])
|| yytext[shortlen]=='_') ++shortlen;
}
if (shortlen) {
// Push rest past numbers for later parse
PARSEP->lexUnputString(yytext + shortlen, yyleng - shortlen);

7
test_regress/t/t_timing_events.v
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@ -28,6 +28,13 @@ module t;
$finish;
end
int x;
initial begin
x = # 1_1 'd 12_34; // Checks we parse _ correctly
if (x != 1234) $stop;
if ($time != 11) $stop;
end
initial #21 $stop; // timeout
endmodule