Parse defparam = as unsupported

src/verilog.y

@@ -3095,6 +3095,8 @@ list_of_defparam_assignments<nodep>:    //== IEEE: list_of_defparam_assignments
 
 defparam_assignment<nodep>:     // ==IEEE: defparam_assignment
                 idAny '.' idAny '=' expr                { $$ = new AstDefParam{$4, *$1, *$3, $5}; }
+        |       idAny '=' expr
+                        { $$ = nullptr; BBUNSUP($2, "Unsupported: defparam with no dot"); }
         |       idAny '.' idAny '.'
                         { $$ = nullptr; BBUNSUP($4, "Unsupported: defparam with more than one dot"); }
         ;

test_regress/t/t_gen_defparam_multi.out

@@ -0,0 +1,17 @@
+%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:14:17: Unsupported: defparam with no dot
+   14 |    defparam PAR = 5;
+      |                 ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:39:24: Unsupported: defparam with more than one dot
+   39 |          defparam m2.m3.PAR3 = 80;
+      |                        ^
+%Error: t/t_gen_defparam_multi.v:39:25: syntax error, unexpected IDENTIFIER, expecting ',' or ';'
+   39 |          defparam m2.m3.PAR3 = 80;
+      |                         ^~~~
+%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:44:24: Unsupported: defparam with more than one dot
+   44 |          defparam m2.m3.PAR3 = 40;
+      |                        ^
+%Error: t/t_gen_defparam_multi.v:44:25: syntax error, unexpected IDENTIFIER, expecting ',' or ';'
+   44 |          defparam m2.m3.PAR3 = 40;
+      |                         ^~~~
+%Error: Exiting due to

test_regress/t/t_gen_defparam_multi.v

@@ -0,0 +1,59 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2012 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   parameter PAR = 3;
+
+   defparam PAR = 5;
+
+   wire [31:0] o2a, o2b, o3a, o3b;
+
+   m1 #(0) m1a(.o2(o2a), .o3(o3a));
+   m1 #(1) m1b(.o2(o2b), .o3(o3b));
+
+   always @ (posedge clk) begin
+      if (PAR != 5) $stop;
+      if (o2a != 8) $stop;
+      if (o2b != 4) $stop;
+      if (o3a != 80) $stop;
+      if (o3b != 40) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module m1 (output wire [31:0] o2,
+           output wire [31:0] o3);
+   parameter W = 0;
+   generate
+      if (W == 0) begin
+         m2 m2 (.*);
+         defparam m2.PAR2 = 8;
+         defparam m2.m3.PAR3 = 80;
+      end
+      else begin
+         m2 m2 (.*);
+         defparam m2.PAR2 = 4;
+         defparam m2.m3.PAR3 = 40;
+      end
+   endgenerate
+endmodule
+
+module m2 (output wire [31:0] o2,
+           output wire [31:0] o3);
+   parameter PAR2 = 20;
+   assign o2 = PAR2;
+   m3 m3 (.*);
+endmodule
+
+module m3 (output wire [31:0] o3);
+   parameter PAR3 = 40;
+   assign o3 = PAR3;
+endmodule

test_regress/t/t_gen_defparam_unsup_bad.out

@@ -1,8 +0,0 @@
-%Error-UNSUPPORTED: t/t_gen_defparam_unsup_bad.v:9:16: Unsupported: defparam with more than one dot
-    9 |    defparam a.b.W = 3;
-      |                ^
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error: t/t_gen_defparam_unsup_bad.v:9:17: syntax error, unexpected IDENTIFIER, expecting ',' or ';'
-    9 |    defparam a.b.W = 3;
-      |                 ^
-%Error: Exiting due to

test_regress/t/t_gen_defparam_unsup_bad.v

@@ -1,18 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2012 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-module t (/*AUTOARG*/);
-   a a ();
-   defparam a.b.W = 3;
-endmodule
-
-module a;
-   b b();
-endmodule
-
-module b;
-   parameter W = 0;
-endmodule