From 36da6a35636bcb47194d6a648fee660db72af9e7 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 15 Mar 2023 21:22:28 -0400
Subject: [PATCH] Fix parsing #1_2 delays

---
 src/verilog.l                    | 5 ++++-
 test_regress/t/t_timing_events.v | 7 +++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/verilog.l b/src/verilog.l
index 8755dd3d8..985f89b6a 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -913,7 +913,10 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
                           /* "# 1'b0" is a delay value so must lex as "#" "1" "'b0" */
                           if (PARSEP->lexPrevToken()=='#') {
                               int shortlen = 0;
-                              while (std::isdigit(yytext[shortlen])) ++shortlen;
+                              if (std::isdigit(yytext[shortlen])) {
+                                  while (std::isdigit(yytext[shortlen])
+                                         || yytext[shortlen]=='_') ++shortlen;
+                              }
                               if (shortlen) {
                                   // Push rest past numbers for later parse
                                   PARSEP->lexUnputString(yytext + shortlen, yyleng - shortlen);
diff --git a/test_regress/t/t_timing_events.v b/test_regress/t/t_timing_events.v
index 24065256b..b9ae56964 100644
--- a/test_regress/t/t_timing_events.v
+++ b/test_regress/t/t_timing_events.v
@@ -28,6 +28,13 @@ module t;
       $finish;
    end
 
+   int         x;
+   initial begin
+      x = # 1_1 'd 12_34;   // Checks we parse _ correctly
+      if (x != 1234) $stop;
+      if ($time != 11) $stop;
+   end
+
    initial #21 $stop; // timeout
 endmodule