2020-03-21 15:24:24 +00:00
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%Warning-WIDTH: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
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2020-03-15 02:02:42 +00:00
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: ... In instance t.sub2
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2020-04-04 00:07:46 +00:00
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18 | wire [0:0] b = a;
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2019-05-31 00:30:59 +00:00
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... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
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2019-05-02 22:45:32 +00:00
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%Error: Exiting due to
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