forked from github/verilator
4 lines
266 B
Plaintext
4 lines
266 B
Plaintext
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%Warning-WIDTH: t/t_lint_repeat_bad.v:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
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%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
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%Error: Exiting due to
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