verilator/test_regress/t/t_trace_complex_structs_fst.out

$date
	Sun Apr 19 04:15:33 2020

$end
$version
	fstWriter
$end
$timescale
	1ps
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc $end
$scope module v_strp $end
$var logic 1 # b1 $end
$var logic 1 $ b0 $end
$upscope $end
$scope module v_strp_strp $end
$scope module x1 $end
$var logic 1 % b1 $end
$var logic 1 & b0 $end
$upscope $end
$scope module x0 $end
$var logic 1 ' b1 $end
$var logic 1 ( b0 $end
$upscope $end
$upscope $end
$scope module v_unip_strp $end
$scope module x1 $end
$var logic 1 ) b1 $end
$var logic 1 * b0 $end
$upscope $end
$scope module x0 $end
$var logic 1 ) b1 $end
$var logic 1 * b0 $end
$upscope $end
$upscope $end
$var logic 2 + v_arrp $end
$var logic 2 , v_arrp_arrp(3) $end
$var logic 2 - v_arrp_arrp(4) $end
$scope module v_arrp_strp(3) $end
$var logic 1 . b1 $end
$var logic 1 / b0 $end
$upscope $end
$scope module v_arrp_strp(4) $end
$var logic 1 0 b1 $end
$var logic 1 1 b0 $end
$upscope $end
$var logic 1 2 v_arru(1) $end
$var logic 1 3 v_arru(2) $end
$var logic 1 4 v_arru_arru(3)(1) $end
$var logic 1 5 v_arru_arru(3)(2) $end
$var logic 1 6 v_arru_arru(4)(1) $end
$var logic 1 7 v_arru_arru(4)(2) $end
$var logic 2 8 v_arru_arrp(3) $end
$var logic 2 9 v_arru_arrp(4) $end
$scope module v_arru_strp(3) $end
$var logic 1 : b1 $end
$var logic 1 ; b0 $end
$upscope $end
$scope module v_arru_strp(4) $end
$var logic 1 < b1 $end
$var logic 1 = b0 $end
$upscope $end
$var real 64 > v_real $end
$var real 64 ? v_arr_real(0) $end
$var real 64 @ v_arr_real(1) $end
$scope module v_str32x2(0) $end
$var logic 32 A data $end
$upscope $end
$scope module v_str32x2(1) $end
$var logic 32 B data $end
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
$upscope $end
$attrbegin misc 07 "" 1 $end
$var logic 32 C v_enumed $end
$attrbegin misc 07 "" 1 $end
$var logic 32 D v_enumed2 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$attrbegin misc 07 "" 2 $end
$var logic 3 E v_enumb $end
$scope module v_enumb2_str $end
$attrbegin misc 07 "" 2 $end
$var logic 3 F a $end
$attrbegin misc 07 "" 2 $end
$var logic 3 G b $end
$upscope $end
$var logic 8 H unpacked_array(-2) $end
$var logic 8 I unpacked_array(-1) $end
$var logic 8 J unpacked_array(0) $end
$scope module unnamedblk1 $end
$var integer 32 K b $end
$scope module unnamedblk2 $end
$var integer 32 L a $end
$upscope $end
$upscope $end
$upscope $end
$scope module $unit $end
$var bit 1 M global_bit $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
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