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Fix tracing -1 index arrays. Closes #2090.

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This commit is contained in:
Wilson Snyder 2020-01-08 07:32:31 -05:00
parent f23fe8fd84
commit 9978cbfa5c
13 changed files with 811 additions and 756 deletions
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2
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@ -32,6 +32,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix huge case statement performance. Closes #1644. [Julien Margetts]
**** Fix tracing -1 index arrays. Closes #2090. [Yutetsu Takatsukasa]
* Verilator 4.024 2019-12-08

5
include/verilated_fst_c.cpp
View File

@ -118,7 +118,7 @@ void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, vluint32_t elem
void VerilatedFst::declSymbol(vluint32_t code, const char* name,
int dtypenum, fstVarDir vardir, fstVarType vartype,
int arraynum, vluint32_t len) {
bool array, int arraynum, vluint32_t len) {
std::pair<Code2SymbolType::iterator, bool> p
= m_code2symbol.insert(std::make_pair(code, static_cast<fstHandle>(NULL)));
std::istringstream nameiss(name);
@ -153,8 +153,7 @@ void VerilatedFst::declSymbol(vluint32_t code, const char* name,
std::stringstream name_ss;
name_ss << symbol_name;
if (arraynum >= 0)
name_ss << "(" << arraynum << ")";
if (array) name_ss << "(" << arraynum << ")";
std::string name_str = name_ss.str();
if (dtypenum > 0) {

26
include/verilated_fst_c.h
View File

@ -60,7 +60,7 @@ private:
VL_UNCOPYABLE(VerilatedFst);
void declSymbol(vluint32_t code, const char* name,
int dtypenum, fstVarDir vardir, fstVarType vartype,
int arraynum, vluint32_t len);
bool array, int arraynum, vluint32_t len);
// helpers
std::vector<char> m_valueStrBuffer;
public:
@ -103,33 +103,33 @@ public:
/// Inside dumping routines, declare a signal
void declBit(vluint32_t code, const char* name,
int dtypenum, fstVarDir vardir, fstVarType vartype,
int arraynum) {
declSymbol(code, name, dtypenum, vardir, vartype, arraynum, 1);
bool array, int arraynum) {
declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, 1);
}
void declBus(vluint32_t code, const char* name,
int dtypenum, fstVarDir vardir, fstVarType vartype,
int arraynum, int msb, int lsb) {
declSymbol(code, name, dtypenum, vardir, vartype, arraynum, msb - lsb + 1);
bool array, int arraynum, int msb, int lsb) {
declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, msb - lsb + 1);
}
void declDouble(vluint32_t code, const char* name,
int dtypenum, fstVarDir vardir, fstVarType vartype,
int arraynum) {
declSymbol(code, name, dtypenum, vardir, vartype, arraynum, 2);
bool array, int arraynum) {
declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, 2);
}
void declFloat(vluint32_t code, const char* name,
int dtypenum, fstVarDir vardir, fstVarType vartype,
int arraynum) {
declSymbol(code, name, dtypenum, vardir, vartype, arraynum, 1);
bool array, int arraynum) {
declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, 1);
}
void declQuad(vluint32_t code, const char* name,
int dtypenum, fstVarDir vardir, fstVarType vartype,
int arraynum, int msb, int lsb) {
declSymbol(code, name, dtypenum, vardir, vartype, arraynum, msb - lsb + 1);
bool array, int arraynum, int msb, int lsb) {
declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, msb - lsb + 1);
}
void declArray(vluint32_t code, const char* name,
int dtypenum, fstVarDir vardir, fstVarType vartype,
int arraynum, int msb, int lsb) {
declSymbol(code, name, dtypenum, vardir, vartype, arraynum, msb - lsb + 1);
bool array, int arraynum, int msb, int lsb) {
declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, msb - lsb + 1);
}
/// Inside dumping routines, dump one signal if it has changed

60
include/verilated_vcd_c.cpp
View File

@ -525,7 +525,7 @@ void VerilatedVcd::module(const std::string& name) {
}
void VerilatedVcd::declare(vluint32_t code, const char* name, const char* wirep,
int arraynum, bool tri, bool bussed, int msb, int lsb) {
bool array, int arraynum, bool tri, bool bussed, int msb, int lsb) {
if (!code) { VL_FATAL_MT(__FILE__, __LINE__, "",
"Internal: internal trace problem, code 0 is illegal"); }
@ -584,7 +584,7 @@ void VerilatedVcd::declare(vluint32_t code, const char* name, const char* wirep,
}
decl += " ";
decl += basename;
if (arraynum>=0) {
if (array) {
sprintf(buf, "(%d)", arraynum);
decl += buf;
hiername += buf;
@ -597,26 +597,42 @@ void VerilatedVcd::declare(vluint32_t code, const char* name, const char* wirep,
m_namemapp->insert(std::make_pair(hiername,decl));
}
void VerilatedVcd::declBit (vluint32_t code, const char* name, int arraynum)
{ declare(code, name, "wire", arraynum, false, false, 0, 0); }
void VerilatedVcd::declBus (vluint32_t code, const char* name, int arraynum, int msb, int lsb)
{ declare(code, name, "wire", arraynum, false, true, msb, lsb); }
void VerilatedVcd::declQuad (vluint32_t code, const char* name, int arraynum, int msb, int lsb)
{ declare(code, name, "wire", arraynum, false, true, msb, lsb); }
void VerilatedVcd::declArray (vluint32_t code, const char* name, int arraynum, int msb, int lsb)
{ declare(code, name, "wire", arraynum, false, true, msb, lsb); }
void VerilatedVcd::declTriBit (vluint32_t code, const char* name, int arraynum)
{ declare(code, name, "wire", arraynum, true, false, 0, 0); }
void VerilatedVcd::declTriBus (vluint32_t code, const char* name, int arraynum, int msb, int lsb)
{ declare(code, name, "wire", arraynum, true, true, msb, lsb); }
void VerilatedVcd::declTriQuad (vluint32_t code, const char* name, int arraynum, int msb, int lsb)
{ declare(code, name, "wire", arraynum, true, true, msb, lsb); }
void VerilatedVcd::declTriArray (vluint32_t code, const char* name, int arraynum, int msb, int lsb)
{ declare(code, name, "wire", arraynum, true, true, msb, lsb); }
void VerilatedVcd::declFloat (vluint32_t code, const char* name, int arraynum)
{ declare(code, name, "real", arraynum, false, false, 31, 0); }
void VerilatedVcd::declDouble (vluint32_t code, const char* name, int arraynum)
{ declare(code, name, "real", arraynum, false, false, 63, 0); }
void VerilatedVcd::declBit(vluint32_t code, const char* name, bool array, int arraynum) {
declare(code, name, "wire", array, arraynum, false, false, 0, 0);
}
void VerilatedVcd::declBus(vluint32_t code, const char* name, bool array, int arraynum, int msb,
int lsb) {
declare(code, name, "wire", array, arraynum, false, true, msb, lsb);
}
void VerilatedVcd::declQuad(vluint32_t code, const char* name, bool array, int arraynum, int msb,
int lsb) {
declare(code, name, "wire", array, arraynum, false, true, msb, lsb);
}
void VerilatedVcd::declArray(vluint32_t code, const char* name, bool array, int arraynum, int msb,
int lsb) {
declare(code, name, "wire", array, arraynum, false, true, msb, lsb);
}
void VerilatedVcd::declTriBit(vluint32_t code, const char* name, bool array, int arraynum) {
declare(code, name, "wire", array, arraynum, true, false, 0, 0);
}
void VerilatedVcd::declTriBus(vluint32_t code, const char* name, bool array, int arraynum, int msb,
int lsb) {
declare(code, name, "wire", array, arraynum, true, true, msb, lsb);
}
void VerilatedVcd::declTriQuad(vluint32_t code, const char* name, bool array, int arraynum,
int msb, int lsb) {
declare(code, name, "wire", array, arraynum, true, true, msb, lsb);
}
void VerilatedVcd::declTriArray(vluint32_t code, const char* name, bool array, int arraynum,
int msb, int lsb) {
declare(code, name, "wire", array, arraynum, true, true, msb, lsb);
}
void VerilatedVcd::declFloat(vluint32_t code, const char* name, bool array, int arraynum) {
declare(code, name, "real", array, arraynum, false, false, 31, 0);
}
void VerilatedVcd::declDouble(vluint32_t code, const char* name, bool array, int arraynum) {
declare(code, name, "real", array, arraynum, false, false, 63, 0);
}
//=============================================================================

24
include/verilated_vcd_c.h
View File

@ -125,8 +125,8 @@ private:
void printStr(const char* str);
void printQuad(vluint64_t n);
void printTime(vluint64_t timeui);
void declare(vluint32_t code, const char* name, const char* wirep,
int arraynum, bool tri, bool bussed, int msb, int lsb);
void declare(vluint32_t code, const char* name, const char* wirep, bool array, int arraynum,
bool tri, bool bussed, int msb, int lsb);
void dumpHeader();
void dumpPrep(vluint64_t timeui);
@ -201,16 +201,16 @@ public:
/// Inside dumping routines, declare a module
void module(const std::string& name);
/// Inside dumping routines, declare a signal
void declBit (vluint32_t code, const char* name, int arraynum);
void declBus (vluint32_t code, const char* name, int arraynum, int msb, int lsb);
void declQuad (vluint32_t code, const char* name, int arraynum, int msb, int lsb);
void declArray (vluint32_t code, const char* name, int arraynum, int msb, int lsb);
void declTriBit (vluint32_t code, const char* name, int arraynum);
void declTriBus (vluint32_t code, const char* name, int arraynum, int msb, int lsb);
void declTriQuad (vluint32_t code, const char* name, int arraynum, int msb, int lsb);
void declTriArray (vluint32_t code, const char* name, int arraynum, int msb, int lsb);
void declDouble (vluint32_t code, const char* name, int arraynum);
void declFloat (vluint32_t code, const char* name, int arraynum);
void declBit( vluint32_t code, const char* name, bool array, int arraynum);
void declBus( vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb);
void declQuad( vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb);
void declArray( vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb);
void declTriBit( vluint32_t code, const char* name, bool array, int arraynum);
void declTriBus( vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb);
void declTriQuad( vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb);
void declTriArray(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb);
void declDouble( vluint32_t code, const char* name, bool array, int arraynum);
void declFloat( vluint32_t code, const char* name, bool array, int arraynum);
// ... other module_start for submodules (based on cell name)
/// Inside dumping routines, dump one signal

10
src/V3EmitC.cpp
View File

@ -3062,13 +3062,13 @@ class EmitCTrace : EmitCStmts {
}
// Range
if (nodep->arrayRange().ranged()) {
puts(",(i+"+cvtToStr(nodep->arrayRange().lo())+")");
puts(", true,(i+" + cvtToStr(nodep->arrayRange().lo()) + ")");
} else {
puts(",-1");
puts(", false,-1");
}
if (!nodep->dtypep()->basicp()->isDouble() // When float/double no longer have widths this can go
&& nodep->bitRange().ranged()) {
puts(","+cvtToStr(nodep->bitRange().left())+","+cvtToStr(nodep->bitRange().right()));
if (!nodep->dtypep()->basicp()->isDouble() && nodep->bitRange().ranged()) {
puts(", " + cvtToStr(nodep->bitRange().left()) + ","
+ cvtToStr(nodep->bitRange().right()));
}
puts(");");
}

368
test_regress/t/t_trace_complex.out
View File

@ -1,49 +1,52 @@
$version Generated by VerilatedVcd $end
$date Wed May 1 19:09:18 2019
$date Wed Jan 8 07:23:20 2020
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 < clk $end
$var wire 1 /" clk $end
$scope module $unit $end
$var wire 1 # global_bit $end
$upscope $end
$scope module t $end
$var wire 1 < clk $end
$var wire 32 $ cyc [31:0] $end
$var real 64 3 v_arr_real(0) $end
$var real 64 5 v_arr_real(1) $end
$var wire 2 * v_arrp [2:1] $end
$var wire 4 + v_arrp_arrp [3:0] $end
$var wire 4 , v_arrp_strp [3:0] $end
$var wire 1 = v_arru(1) $end
$var wire 1 > v_arru(2) $end
$var wire 2 - v_arru_arrp(3) [2:1] $end
$var wire 2 . v_arru_arrp(4) [2:1] $end
$var wire 1 ? v_arru_arru(3)(1) $end
$var wire 1 @ v_arru_arru(3)(2) $end
$var wire 1 A v_arru_arru(4)(1) $end
$var wire 1 B v_arru_arru(4)(2) $end
$var wire 2 / v_arru_strp(3) [1:0] $end
$var wire 2 0 v_arru_strp(4) [1:0] $end
$var wire 3 9 v_enumb [2:0] $end
$var wire 32 7 v_enumed [31:0] $end
$var wire 32 8 v_enumed2 [31:0] $end
$var real 64 1 v_real $end
$var wire 64 % v_str32x2 [63:0] $end
$var wire 2 ' v_strp [1:0] $end
$var wire 4 ( v_strp_strp [3:0] $end
$var wire 2 ) v_unip_strp [1:0] $end
$var wire 1 /" clk $end
$var wire 32 + cyc [31:0] $end
$var wire 8 h" unpacked_array(-1) [7:0] $end
$var wire 8 g" unpacked_array(-2) [7:0] $end
$var wire 8 i" unpacked_array(0) [7:0] $end
$var real 64 E! v_arr_real(0) $end
$var real 64 G! v_arr_real(1) $end
$var wire 2 [ v_arrp [2:1] $end
$var wire 4 c v_arrp_arrp [3:0] $end
$var wire 4 k v_arrp_strp [3:0] $end
$var wire 1 7" v_arru(1) $end
$var wire 1 8" v_arru(2) $end
$var wire 2 s v_arru_arrp(3) [2:1] $end
$var wire 2 t v_arru_arrp(4) [2:1] $end
$var wire 1 G" v_arru_arru(3)(1) $end
$var wire 1 O" v_arru_arru(3)(2) $end
$var wire 1 W" v_arru_arru(4)(1) $end
$var wire 1 _" v_arru_arru(4)(2) $end
$var wire 2 %! v_arru_strp(3) [1:0] $end
$var wire 2 -! v_arru_strp(4) [1:0] $end
$var wire 3 u! v_enumb [2:0] $end
$var wire 32 e! v_enumed [31:0] $end
$var wire 32 m! v_enumed2 [31:0] $end
$var real 64 5! v_real $end
$var wire 64 3 v_str32x2 [63:0] $end
$var wire 2 C v_strp [1:0] $end
$var wire 4 K v_strp_strp [3:0] $end
$var wire 2 S v_unip_strp [1:0] $end
$scope module p2 $end
$var wire 32 C PARAM [31:0] $end
$var wire 32 !# PARAM [31:0] $end
$upscope $end
$scope module p3 $end
$var wire 32 D PARAM [31:0] $end
$var wire 32 )# PARAM [31:0] $end
$upscope $end
$scope module unnamedblk1 $end
$var wire 32 : b [31:0] $end
$var wire 32 }! b [31:0] $end
$scope module unnamedblk2 $end
$var wire 32 ; a [31:0] $end
$var wire 32 '" a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
@ -53,164 +56,167 @@ $enddefinitions $end
#0
1#
b00000000000000000000000000000000 $
b0000000000000000000000000000000000000000000000000000000011111111 %
b00 '
b0000 (
b00 )
b00 *
b0000 +
b0000 ,
b00 -
b00 .
b00 /
b00 0
r0 1
r0 3
r0 5
b00000000000000000000000000000000 7
b00000000000000000000000000000000 8
b000 9
b00000000000000000000000000000000 :
b00000000000000000000000000000000 ;
0<
0=
0>
0?
0@
0A
0B
b00000000000000000000000000000010 C
b00000000000000000000000000000011 D
b00000000000000000000000000000000 +
b0000000000000000000000000000000000000000000000000000000011111111 3
b00 C
b0000 K
b00 S
b00 [
b0000 c
b0000 k
b00 s
b00 t
b00 %!
b00 -!
r0 5!
r0 E!
r0 G!
b00000000000000000000000000000000 e!
b00000000000000000000000000000000 m!
b000 u!
b00000000000000000000000000000000 }!
b00000000000000000000000000000000 '"
0/"
07"
08"
0G"
0O"
0W"
0_"
b00000000 g"
b00000000 h"
b00000000 i"
b00000000000000000000000000000010 !#
b00000000000000000000000000000011 )#
#10
b00000000000000000000000000000001 $
b0000000000000000000000000000000100000000000000000000000011111110 %
b11 '
b1111 (
b11 )
b11 *
b1111 +
b1111 ,
b11 -
b11 .
b11 /
b11 0
r0.1 1
r0.2 3
r0.3 5
b00000000000000000000000000000001 7
b00000000000000000000000000000010 8
b111 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;
1<
b00000000000000000000000000000001 +
b0000000000000000000000000000000100000000000000000000000011111110 3
b11 C
b1111 K
b11 S
b11 [
b1111 c
b1111 k
b11 s
b11 t
b11 %!
b11 -!
r0.1 5!
r0.2 E!
r0.3 G!
b00000000000000000000000000000001 e!
b00000000000000000000000000000010 m!
b111 u!
b00000000000000000000000000000101 }!
b00000000000000000000000000000101 '"
1/"
#15
0<
0/"
#20
b00000000000000000000000000000010 $
b0000000000000000000000000000001000000000000000000000000011111101 %
b00 '
b0000 (
b00 )
b00 *
b0000 +
b0000 ,
b00 -
b00 .
b00 /
b00 0
r0.2 1
r0.4 3
r0.6 5
b00000000000000000000000000000010 7
b00000000000000000000000000000100 8
b110 9
1<
b00000000000000000000000000000010 +
b0000000000000000000000000000001000000000000000000000000011111101 3
b00 C
b0000 K
b00 S
b00 [
b0000 c
b0000 k
b00 s
b00 t
b00 %!
b00 -!
r0.2 5!
r0.4 E!
r0.6 G!
b00000000000000000000000000000010 e!
b00000000000000000000000000000100 m!
b110 u!
1/"
#25
0<
0/"
#30
b00000000000000000000000000000011 $
b0000000000000000000000000000001100000000000000000000000011111100 %
b11 '
b1111 (
b11 )
b11 *
b1111 +
b1111 ,
b11 -
b11 .
b11 /
b11 0
r0.3 1
r0.6000000000000001 3
r0.8999999999999999 5
b00000000000000000000000000000011 7
b00000000000000000000000000000110 8
b101 9
1<
b00000000000000000000000000000011 +
b0000000000000000000000000000001100000000000000000000000011111100 3
b11 C
b1111 K
b11 S
b11 [
b1111 c
b1111 k
b11 s
b11 t
b11 %!
b11 -!
r0.3 5!
r0.6000000000000001 E!
r0.8999999999999999 G!
b00000000000000000000000000000011 e!
b00000000000000000000000000000110 m!
b101 u!
1/"
#35
0<
0/"
#40
b00000000000000000000000000000100 $
b0000000000000000000000000000010000000000000000000000000011111011 %
b00 '
b0000 (
b00 )
b00 *
b0000 +
b0000 ,
b00 -
b00 .
b00 /
b00 0
r0.4 1
r0.8 3
r1.2 5
b00000000000000000000000000000100 7
b00000000000000000000000000001000 8
b100 9
1<
b00000000000000000000000000000100 +
b0000000000000000000000000000010000000000000000000000000011111011 3
b00 C
b0000 K
b00 S
b00 [
b0000 c
b0000 k
b00 s
b00 t
b00 %!
b00 -!
r0.4 5!
r0.8 E!
r1.2 G!
b00000000000000000000000000000100 e!
b00000000000000000000000000001000 m!
b100 u!
1/"
#45
0<
0/"
#50
b00000000000000000000000000000101 $
b0000000000000000000000000000010100000000000000000000000011111010 %
b11 '
b1111 (
b11 )
b11 *
b1111 +
b1111 ,
b11 -
b11 .
b11 /
b11 0
r0.5 1
r1 3
r1.5 5
b00000000000000000000000000000101 7
b00000000000000000000000000001010 8
b011 9
1<
b00000000000000000000000000000101 +
b0000000000000000000000000000010100000000000000000000000011111010 3
b11 C
b1111 K
b11 S
b11 [
b1111 c
b1111 k
b11 s
b11 t
b11 %!
b11 -!
r0.5 5!
r1 E!
r1.5 G!
b00000000000000000000000000000101 e!
b00000000000000000000000000001010 m!
b011 u!
1/"
#55
0<
0/"
#60
b00000000000000000000000000000110 $
b0000000000000000000000000000011000000000000000000000000011111001 %
b00 '
b0000 (
b00 )
b00 *
b0000 +
b0000 ,
b00 -
b00 .
b00 /
b00 0
r0.6 1
r1.2 3
r1.8 5
b00000000000000000000000000000110 7
b00000000000000000000000000001100 8
b010 9
1<
b00000000000000000000000000000110 +
b0000000000000000000000000000011000000000000000000000000011111001 3
b00 C
b0000 K
b00 S
b00 [
b0000 c
b0000 k
b00 s
b00 t
b00 %!
b00 -!
r0.6 5!
r1.2 E!
r1.8 G!
b00000000000000000000000000000110 e!
b00000000000000000000000000001100 m!
b010 u!
1/"

2
test_regress/t/t_trace_complex.v
View File

@ -65,6 +65,8 @@ module t (clk);
typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t;
enumb_t v_enumb;
logic [7:0] unpacked_array[-2:0];
p #(.PARAM(2)) p2 ();
p #(.PARAM(3)) p3 ();

52
test_regress/t/t_trace_complex_fst.out
View File

@ -1,5 +1,5 @@
$date
Wed May 1 19:09:18 2019
Wed Jan 8 07:26:16 2020
$end
$version
@ -41,21 +41,24 @@ $var logic 32 8 v_enumed2 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$attrbegin misc 07 "" 2 $end
$var logic 3 9 v_enumb $end
$var logic 8 : unpacked_array(-2) $end
$var logic 8 ; unpacked_array(-1) $end
$var logic 8 < unpacked_array(0) $end
$scope module unnamedblk1 $end
$var integer 32 : b $end
$var integer 32 = b $end
$scope module unnamedblk2 $end
$var integer 32 ; a $end
$var integer 32 > a $end
$upscope $end
$upscope $end
$scope module p2 $end
$var parameter 32 < PARAM $end
$var parameter 32 ? PARAM $end
$upscope $end
$scope module p3 $end
$var parameter 32 = PARAM $end
$var parameter 32 @ PARAM $end
$upscope $end
$upscope $end
$scope module $unit $end
$var bit 1 > global_bit $end
$var bit 1 A global_bit $end
$upscope $end
$upscope $end
$enddefinitions $end
@ -85,14 +88,17 @@ b0000000000000000000000000000000000000000000000000000000011111111 6
b00000000000000000000000000000000 7
b00000000000000000000000000000000 8
b000 9
b00000000000000000000000000000000 :
b00000000000000000000000000000000 ;
b00000000000000000000000000000010 <
b00000000000000000000000000000011 =
1>
b00000000 :
b00000000 ;
b00000000 <
b00000000000000000000000000000000 =
b00000000000000000000000000000000 >
b00000000000000000000000000000010 ?
b00000000000000000000000000000011 @
1A
#10
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 :
b00000000000000000000000000000101 >
b00000000000000000000000000000101 =
b111 9
b00000000000000000000000000000010 8
b00000000000000000000000000000001 7
@ -134,14 +140,14 @@ b0000000000000000000000000000001000000000000000000000000011111101 6
b00000000000000000000000000000010 7
b00000000000000000000000000000100 8
b110 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 =
b00000000000000000000000000000101 >
#25
0!
#30
1!
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 :
b00000000000000000000000000000101 >
b00000000000000000000000000000101 =
b101 9
b00000000000000000000000000000110 8
b00000000000000000000000000000011 7
@ -182,14 +188,14 @@ b0000000000000000000000000000010000000000000000000000000011111011 6
b00000000000000000000000000000100 7
b00000000000000000000000000001000 8
b100 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 =
b00000000000000000000000000000101 >
#45
0!
#50
1!
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 :
b00000000000000000000000000000101 >
b00000000000000000000000000000101 =
b011 9
b00000000000000000000000000001010 8
b00000000000000000000000000000101 7
@ -230,5 +236,5 @@ b0000000000000000000000000000011000000000000000000000000011111001 6
b00000000000000000000000000000110 7
b00000000000000000000000000001100 8
b010 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 =
b00000000000000000000000000000101 >

368
test_regress/t/t_trace_complex_params.out
View File

@ -1,49 +1,52 @@
$version Generated by VerilatedVcd $end
$date Wed May 1 19:09:21 2019
$date Wed Jan 8 07:26:16 2020
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 < clk $end
$var wire 1 /" clk $end
$scope module $unit $end
$var wire 1 # global_bit $end
$upscope $end
$scope module t $end
$var wire 1 < clk $end
$var wire 32 $ cyc [31:0] $end
$var real 64 3 v_arr_real(0) $end
$var real 64 5 v_arr_real(1) $end
$var wire 2 * v_arrp [2:1] $end
$var wire 4 + v_arrp_arrp [3:0] $end
$var wire 4 , v_arrp_strp [3:0] $end
$var wire 1 = v_arru(1) $end
$var wire 1 > v_arru(2) $end
$var wire 2 - v_arru_arrp(3) [2:1] $end
$var wire 2 . v_arru_arrp(4) [2:1] $end
$var wire 1 ? v_arru_arru(3)(1) $end
$var wire 1 @ v_arru_arru(3)(2) $end
$var wire 1 A v_arru_arru(4)(1) $end
$var wire 1 B v_arru_arru(4)(2) $end
$var wire 2 / v_arru_strp(3) [1:0] $end
$var wire 2 0 v_arru_strp(4) [1:0] $end
$var wire 3 9 v_enumb [2:0] $end
$var wire 32 7 v_enumed [31:0] $end
$var wire 32 8 v_enumed2 [31:0] $end
$var real 64 1 v_real $end
$var wire 64 % v_str32x2 [63:0] $end
$var wire 2 ' v_strp [1:0] $end
$var wire 4 ( v_strp_strp [3:0] $end
$var wire 2 ) v_unip_strp [1:0] $end
$var wire 1 /" clk $end
$var wire 32 + cyc [31:0] $end
$var wire 8 h" unpacked_array(-1) [7:0] $end
$var wire 8 g" unpacked_array(-2) [7:0] $end
$var wire 8 i" unpacked_array(0) [7:0] $end
$var real 64 E! v_arr_real(0) $end
$var real 64 G! v_arr_real(1) $end
$var wire 2 [ v_arrp [2:1] $end
$var wire 4 c v_arrp_arrp [3:0] $end
$var wire 4 k v_arrp_strp [3:0] $end
$var wire 1 7" v_arru(1) $end
$var wire 1 8" v_arru(2) $end
$var wire 2 s v_arru_arrp(3) [2:1] $end
$var wire 2 t v_arru_arrp(4) [2:1] $end
$var wire 1 G" v_arru_arru(3)(1) $end
$var wire 1 O" v_arru_arru(3)(2) $end
$var wire 1 W" v_arru_arru(4)(1) $end
$var wire 1 _" v_arru_arru(4)(2) $end
$var wire 2 %! v_arru_strp(3) [1:0] $end
$var wire 2 -! v_arru_strp(4) [1:0] $end
$var wire 3 u! v_enumb [2:0] $end
$var wire 32 e! v_enumed [31:0] $end
$var wire 32 m! v_enumed2 [31:0] $end
$var real 64 5! v_real $end
$var wire 64 3 v_str32x2 [63:0] $end
$var wire 2 C v_strp [1:0] $end
$var wire 4 K v_strp_strp [3:0] $end
$var wire 2 S v_unip_strp [1:0] $end
$scope module p2 $end
$var wire 32 C PARAM [31:0] $end
$var wire 32 !# PARAM [31:0] $end
$upscope $end
$scope module p3 $end
$var wire 32 D PARAM [31:0] $end
$var wire 32 )# PARAM [31:0] $end
$upscope $end
$scope module unnamedblk1 $end
$var wire 32 : b [31:0] $end
$var wire 32 }! b [31:0] $end
$scope module unnamedblk2 $end
$var wire 32 ; a [31:0] $end
$var wire 32 '" a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
@ -53,164 +56,167 @@ $enddefinitions $end
#0
1#
b00000000000000000000000000000000 $
b0000000000000000000000000000000000000000000000000000000011111111 %
b00 '
b0000 (
b00 )
b00 *
b0000 +
b0000 ,
b00 -
b00 .
b00 /
b00 0
r0 1
r0 3
r0 5
b00000000000000000000000000000000 7
b00000000000000000000000000000000 8
b000 9
b00000000000000000000000000000000 :
b00000000000000000000000000000000 ;
0<
0=
0>
0?
0@
0A
0B
b00000000000000000000000000000010 C
b00000000000000000000000000000011 D
b00000000000000000000000000000000 +
b0000000000000000000000000000000000000000000000000000000011111111 3
b00 C
b0000 K
b00 S
b00 [
b0000 c
b0000 k
b00 s
b00 t
b00 %!
b00 -!
r0 5!
r0 E!
r0 G!
b00000000000000000000000000000000 e!
b00000000000000000000000000000000 m!
b000 u!
b00000000000000000000000000000000 }!
b00000000000000000000000000000000 '"
0/"
07"
08"
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0_"
b00000000 g"
b00000000 h"
b00000000 i"
b00000000000000000000000000000010 !#
b00000000000000000000000000000011 )#
#10
b00000000000000000000000000000001 $
b0000000000000000000000000000000100000000000000000000000011111110 %
b11 '
b1111 (
b11 )
b11 *
b1111 +
b1111 ,
b11 -
b11 .
b11 /
b11 0
r0.1 1
r0.2 3
r0.3 5
b00000000000000000000000000000001 7
b00000000000000000000000000000010 8
b111 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;
1<
b00000000000000000000000000000001 +
b0000000000000000000000000000000100000000000000000000000011111110 3
b11 C
b1111 K
b11 S
b11 [
b1111 c
b1111 k
b11 s
b11 t
b11 %!
b11 -!
r0.1 5!
r0.2 E!
r0.3 G!
b00000000000000000000000000000001 e!
b00000000000000000000000000000010 m!
b111 u!
b00000000000000000000000000000101 }!
b00000000000000000000000000000101 '"
1/"
#15
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b00000000000000000000000000000010 $
b0000000000000000000000000000001000000000000000000000000011111101 %
b00 '
b0000 (
b00 )
b00 *
b0000 +
b0000 ,
b00 -
b00 .
b00 /
b00 0
r0.2 1
r0.4 3
r0.6 5
b00000000000000000000000000000010 7
b00000000000000000000000000000100 8
b110 9
1<
b00000000000000000000000000000010 +
b0000000000000000000000000000001000000000000000000000000011111101 3
b00 C
b0000 K
b00 S
b00 [
b0000 c
b0000 k
b00 s
b00 t
b00 %!
b00 -!
r0.2 5!
r0.4 E!
r0.6 G!
b00000000000000000000000000000010 e!
b00000000000000000000000000000100 m!
b110 u!
1/"
#25
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b00000000000000000000000000000011 $
b0000000000000000000000000000001100000000000000000000000011111100 %
b11 '
b1111 (
b11 )
b11 *
b1111 +
b1111 ,
b11 -
b11 .
b11 /
b11 0
r0.3 1
r0.6000000000000001 3
r0.8999999999999999 5
b00000000000000000000000000000011 7
b00000000000000000000000000000110 8
b101 9
1<
b00000000000000000000000000000011 +
b0000000000000000000000000000001100000000000000000000000011111100 3
b11 C
b1111 K
b11 S
b11 [
b1111 c
b1111 k
b11 s
b11 t
b11 %!
b11 -!
r0.3 5!
r0.6000000000000001 E!
r0.8999999999999999 G!
b00000000000000000000000000000011 e!
b00000000000000000000000000000110 m!
b101 u!
1/"
#35
0<
0/"
#40
b00000000000000000000000000000100 $
b0000000000000000000000000000010000000000000000000000000011111011 %
b00 '
b0000 (
b00 )
b00 *
b0000 +
b0000 ,
b00 -
b00 .
b00 /
b00 0
r0.4 1
r0.8 3
r1.2 5
b00000000000000000000000000000100 7
b00000000000000000000000000001000 8
b100 9
1<
b00000000000000000000000000000100 +
b0000000000000000000000000000010000000000000000000000000011111011 3
b00 C
b0000 K
b00 S
b00 [
b0000 c
b0000 k
b00 s
b00 t
b00 %!
b00 -!
r0.4 5!
r0.8 E!
r1.2 G!
b00000000000000000000000000000100 e!
b00000000000000000000000000001000 m!
b100 u!
1/"
#45
0<
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#50
b00000000000000000000000000000101 $
b0000000000000000000000000000010100000000000000000000000011111010 %
b11 '
b1111 (
b11 )
b11 *
b1111 +
b1111 ,
b11 -
b11 .
b11 /
b11 0
r0.5 1
r1 3
r1.5 5
b00000000000000000000000000000101 7
b00000000000000000000000000001010 8
b011 9
1<
b00000000000000000000000000000101 +
b0000000000000000000000000000010100000000000000000000000011111010 3
b11 C
b1111 K
b11 S
b11 [
b1111 c
b1111 k
b11 s
b11 t
b11 %!
b11 -!
r0.5 5!
r1 E!
r1.5 G!
b00000000000000000000000000000101 e!
b00000000000000000000000000001010 m!
b011 u!
1/"
#55
0<
0/"
#60
b00000000000000000000000000000110 $
b0000000000000000000000000000011000000000000000000000000011111001 %
b00 '
b0000 (
b00 )
b00 *
b0000 +
b0000 ,
b00 -
b00 .
b00 /
b00 0
r0.6 1
r1.2 3
r1.8 5
b00000000000000000000000000000110 7
b00000000000000000000000000001100 8
b010 9
1<
b00000000000000000000000000000110 +
b0000000000000000000000000000011000000000000000000000000011111001 3
b00 C
b0000 K
b00 S
b00 [
b0000 c
b0000 k
b00 s
b00 t
b00 %!
b00 -!
r0.6 5!
r1.2 E!
r1.8 G!
b00000000000000000000000000000110 e!
b00000000000000000000000000001100 m!
b010 u!
1/"

52
test_regress/t/t_trace_complex_params_fst.out
View File

@ -1,5 +1,5 @@
$date
Wed May 1 19:09:23 2019
Wed Jan 8 07:26:17 2020
$end
$version
@ -41,21 +41,24 @@ $var logic 32 8 v_enumed2 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$attrbegin misc 07 "" 2 $end
$var logic 3 9 v_enumb $end
$var logic 8 : unpacked_array(-2) $end
$var logic 8 ; unpacked_array(-1) $end
$var logic 8 < unpacked_array(0) $end
$scope module unnamedblk1 $end
$var integer 32 : b $end
$var integer 32 = b $end
$scope module unnamedblk2 $end
$var integer 32 ; a $end
$var integer 32 > a $end
$upscope $end
$upscope $end
$scope module p2 $end
$var parameter 32 < PARAM $end
$var parameter 32 ? PARAM $end
$upscope $end
$scope module p3 $end
$var parameter 32 = PARAM $end
$var parameter 32 @ PARAM $end
$upscope $end
$upscope $end
$scope module $unit $end
$var bit 1 > global_bit $end
$var bit 1 A global_bit $end
$upscope $end
$upscope $end
$enddefinitions $end
@ -85,14 +88,17 @@ b0000000000000000000000000000000000000000000000000000000011111111 6
b00000000000000000000000000000000 7
b00000000000000000000000000000000 8
b000 9
b00000000000000000000000000000000 :
b00000000000000000000000000000000 ;
b00000000000000000000000000000010 <
b00000000000000000000000000000011 =
1>
b00000000 :
b00000000 ;
b00000000 <
b00000000000000000000000000000000 =
b00000000000000000000000000000000 >
b00000000000000000000000000000010 ?
b00000000000000000000000000000011 @
1A
#10
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 :
b00000000000000000000000000000101 >
b00000000000000000000000000000101 =
b111 9
b00000000000000000000000000000010 8
b00000000000000000000000000000001 7
@ -134,14 +140,14 @@ b0000000000000000000000000000001000000000000000000000000011111101 6
b00000000000000000000000000000010 7
b00000000000000000000000000000100 8
b110 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 =
b00000000000000000000000000000101 >
#25
0!
#30
1!
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 :
b00000000000000000000000000000101 >
b00000000000000000000000000000101 =
b101 9
b00000000000000000000000000000110 8
b00000000000000000000000000000011 7
@ -182,14 +188,14 @@ b0000000000000000000000000000010000000000000000000000000011111011 6
b00000000000000000000000000000100 7
b00000000000000000000000000001000 8
b100 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 =
b00000000000000000000000000000101 >
#45
0!
#50
1!
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 :
b00000000000000000000000000000101 >
b00000000000000000000000000000101 =
b011 9
b00000000000000000000000000001010 8
b00000000000000000000000000000101 7
@ -230,5 +236,5 @@ b0000000000000000000000000000011000000000000000000000000011111001 6
b00000000000000000000000000000110 7
b00000000000000000000000000001100 8
b010 9
b00000000000000000000000000000101 :
b00000000000000000000000000000101 ;
b00000000000000000000000000000101 =
b00000000000000000000000000000101 >

554
test_regress/t/t_trace_complex_structs.out
View File

@ -1,83 +1,86 @@
$version Generated by VerilatedVcd $end
$date Wed May 1 19:09:26 2019
$date Wed Jan 8 07:26:19 2020
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 G clk $end
$var wire 1 )# clk $end
$scope module $unit $end
$var wire 1 # global_bit $end
$upscope $end
$scope module t $end
$var wire 1 G clk $end
$var wire 32 $ cyc [31:0] $end
$var real 64 > v_arr_real(0) $end
$var real 64 @ v_arr_real(1) $end
$var wire 2 / v_arrp [2:1] $end
$var wire 2 0 v_arrp_arrp(3) [1:0] $end
$var wire 2 1 v_arrp_arrp(4) [1:0] $end
$var wire 1 H v_arru(1) $end
$var wire 1 I v_arru(2) $end
$var wire 2 6 v_arru_arrp(3) [2:1] $end
$var wire 2 7 v_arru_arrp(4) [2:1] $end
$var wire 1 J v_arru_arru(3)(1) $end
$var wire 1 K v_arru_arru(3)(2) $end
$var wire 1 L v_arru_arru(4)(1) $end
$var wire 1 M v_arru_arru(4)(2) $end
$var wire 3 D v_enumb [2:0] $end
$var wire 32 B v_enumed [31:0] $end
$var wire 32 C v_enumed2 [31:0] $end
$var real 64 < v_real $end
$var wire 1 )# clk $end
$var wire 32 + cyc [31:0] $end
$var wire 8 b# unpacked_array(-1) [7:0] $end
$var wire 8 a# unpacked_array(-2) [7:0] $end
$var wire 8 c# unpacked_array(0) [7:0] $end
$var real 64 ?" v_arr_real(0) $end
$var real 64 A" v_arr_real(1) $end
$var wire 2 %! v_arrp [2:1] $end
$var wire 2 -! v_arrp_arrp(3) [1:0] $end
$var wire 2 5! v_arrp_arrp(4) [1:0] $end
$var wire 1 1# v_arru(1) $end
$var wire 1 2# v_arru(2) $end
$var wire 2 ]! v_arru_arrp(3) [2:1] $end
$var wire 2 ^! v_arru_arrp(4) [2:1] $end
$var wire 1 A# v_arru_arru(3)(1) $end
$var wire 1 I# v_arru_arru(3)(2) $end
$var wire 1 Q# v_arru_arru(4)(1) $end
$var wire 1 Y# v_arru_arru(4)(2) $end
$var wire 3 o" v_enumb [2:0] $end
$var wire 32 _" v_enumed [31:0] $end
$var wire 32 g" v_enumed2 [31:0] $end
$var real 64 /" v_real $end
$scope module unnamedblk1 $end
$var wire 32 E b [31:0] $end
$var wire 32 w" b [31:0] $end
$scope module unnamedblk2 $end
$var wire 32 F a [31:0] $end
$var wire 32 !# a [31:0] $end
$upscope $end
$upscope $end
$scope module v_arrp_strp(3) $end
$var wire 1 3 b0 $end
$var wire 1 2 b1 $end
$var wire 1 E! b0 $end
$var wire 1 =! b1 $end
$upscope $end
$scope module v_arrp_strp(4) $end
$var wire 1 5 b0 $end
$var wire 1 4 b1 $end
$var wire 1 U! b0 $end
$var wire 1 M! b1 $end
$upscope $end
$scope module v_arru_strp(3) $end
$var wire 1 9 b0 $end
$var wire 1 8 b1 $end
$var wire 1 u! b0 $end
$var wire 1 m! b1 $end
$upscope $end
$scope module v_arru_strp(4) $end
$var wire 1 ; b0 $end
$var wire 1 : b1 $end
$var wire 1 '" b0 $end
$var wire 1 }! b1 $end
$upscope $end
$scope module v_str32x2(0) $end
$var wire 32 % data [31:0] $end
$var wire 32 3 data [31:0] $end
$upscope $end
$scope module v_str32x2(1) $end
$var wire 32 & data [31:0] $end
$var wire 32 ; data [31:0] $end
$upscope $end
$scope module v_strp $end
$var wire 1 ( b0 $end
$var wire 1 ' b1 $end
$var wire 1 K b0 $end
$var wire 1 C b1 $end
$upscope $end
$scope module v_strp_strp $end
$scope module x0 $end
$var wire 1 , b0 $end
$var wire 1 + b1 $end
$var wire 1 k b0 $end
$var wire 1 c b1 $end
$upscope $end
$scope module x1 $end
$var wire 1 * b0 $end
$var wire 1 ) b1 $end
$var wire 1 [ b0 $end
$var wire 1 S b1 $end
$upscope $end
$upscope $end
$scope module v_unip_strp $end
$scope module x0 $end
$var wire 1 . b0 $end
$var wire 1 - b1 $end
$var wire 1 { b0 $end
$var wire 1 s b1 $end
$upscope $end
$scope module x1 $end
$var wire 1 . b0 $end
$var wire 1 - b1 $end
$var wire 1 { b0 $end
$var wire 1 s b1 $end
$upscope $end
$upscope $end
$upscope $end
@ -87,246 +90,249 @@ $enddefinitions $end
#0
1#
b00000000000000000000000000000000 $
b00000000000000000000000011111111 %
b00000000000000000000000000000000 &
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b00000000000000000000000000000001 B
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b00000000000000000000000000001000 C
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44
test_regress/t/t_trace_complex_structs_fst.out
View File

@ -1,5 +1,5 @@
$date
Wed May 1 19:09:29 2019
Wed Jan 8 07:26:20 2020
$end
$version
@ -81,15 +81,18 @@ $var logic 32 D v_enumed2 $end
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
$attrbegin misc 07 "" 2 $end
$var logic 3 E v_enumb $end
$var logic 8 F unpacked_array(-2) $end
$var logic 8 G unpacked_array(-1) $end
$var logic 8 H unpacked_array(0) $end
$scope module unnamedblk1 $end
$var integer 32 F b $end
$var integer 32 I b $end
$scope module unnamedblk2 $end
$var integer 32 G a $end
$var integer 32 J a $end
$upscope $end
$upscope $end
$upscope $end
$scope module $unit $end
$var bit 1 H global_bit $end
$var bit 1 K global_bit $end
$upscope $end
$upscope $end
$enddefinitions $end
@ -131,12 +134,15 @@ b00000000000000000000000000000000 B
b00000000000000000000000000000000 C
b00000000000000000000000000000000 D
b000 E
b00000000000000000000000000000000 F
b00000000000000000000000000000000 G
1H
b00000000 F
b00000000 G
b00000000 H
b00000000000000000000000000000000 I
b00000000000000000000000000000000 J
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#10
b00000000000000000000000000000101 G
b00000000000000000000000000000101 F
b00000000000000000000000000000101 J
b00000000000000000000000000000101 I
b111 E
b00000000000000000000000000000010 D
b00000000000000000000000000000001 C
@ -202,14 +208,14 @@ b00000000000000000000000000000010 B
b00000000000000000000000000000010 C
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b00000000000000000000000000000101 F
b00000000000000000000000000000101 G
b00000000000000000000000000000101 I
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b00000000000000000000000000000011 C
@ -274,14 +280,14 @@ b00000000000000000000000000000100 B
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@ -346,5 +352,5 @@ b00000000000000000000000000000110 B
b00000000000000000000000000000110 C
b00000000000000000000000000001100 D
b010 E
b00000000000000000000000000000101 F
b00000000000000000000000000000101 G
b00000000000000000000000000000101 I
b00000000000000000000000000000101 J