forked from github/verilator
Fix FST enums not displaying, bug1426.
This commit is contained in:
parent
08d041cb93
commit
3acb85a005
2
Changes
2
Changes
@ -16,6 +16,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix GTKWave register warning, bug1421. [Pieter Kapsenberg]
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**** Fix FST enums not displaying, bug1426. [Danilo Ramos]
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* Verilator 4.012 2019-3-23
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@ -230,6 +230,10 @@ private:
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}
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insureCleanAndNext(nodep->bodysp());
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}
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virtual void visit(AstTraceDecl* nodep) {
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// No cleaning, or would loose pointer to enum
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iterateChildren(nodep);
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}
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virtual void visit(AstTraceInc* nodep) {
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iterateChildren(nodep);
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insureCleanAndNext(nodep->valuep());
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@ -2956,7 +2956,7 @@ class EmitCTrace : EmitCStmts {
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// Return enum number or -1 for none
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if (v3Global.opt.traceFormat() == TraceFormat::FST) {
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// Skip over refs-to-refs, but stop before final ref so can get data type name
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// Alternatively back in V3Width we could have push enum names from upper typedefs
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// Alternatively back in V3Width we could push enum names from upper typedefs
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if (AstEnumDType* enump = VN_CAST(nodep->skipRefToEnump(), EnumDType)) {
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int enumNum = enump->user1();
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if (!enumNum) {
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@ -1,31 +1,32 @@
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$version Generated by VerilatedVcd $end
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$date Sun Oct 7 21:58:06 2018
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$date Wed May 1 19:09:18 2019
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 ; clk $end
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$var wire 1 < clk $end
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$scope module $unit $end
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$var wire 1 # global_bit $end
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$upscope $end
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$scope module t $end
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$var wire 1 ; clk $end
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$var wire 1 < clk $end
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$var wire 32 $ cyc [31:0] $end
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$var real 64 3 v_arr_real(0) $end
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$var real 64 5 v_arr_real(1) $end
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$var wire 2 * v_arrp [2:1] $end
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$var wire 4 + v_arrp_arrp [3:0] $end
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$var wire 4 , v_arrp_strp [3:0] $end
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$var wire 1 < v_arru(1) $end
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$var wire 1 = v_arru(2) $end
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$var wire 1 = v_arru(1) $end
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$var wire 1 > v_arru(2) $end
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$var wire 2 - v_arru_arrp(3) [2:1] $end
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$var wire 2 . v_arru_arrp(4) [2:1] $end
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$var wire 1 > v_arru_arru(3)(1) $end
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$var wire 1 ? v_arru_arru(3)(2) $end
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$var wire 1 @ v_arru_arru(4)(1) $end
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$var wire 1 A v_arru_arru(4)(2) $end
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$var wire 1 ? v_arru_arru(3)(1) $end
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$var wire 1 @ v_arru_arru(3)(2) $end
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$var wire 1 A v_arru_arru(4)(1) $end
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$var wire 1 B v_arru_arru(4)(2) $end
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$var wire 2 / v_arru_strp(3) [1:0] $end
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$var wire 2 0 v_arru_strp(4) [1:0] $end
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$var wire 3 9 v_enumb [2:0] $end
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$var wire 32 7 v_enumed [31:0] $end
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$var wire 32 8 v_enumed2 [31:0] $end
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$var real 64 1 v_real $end
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@ -34,15 +35,15 @@ $timescale 1ns $end
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$var wire 4 ( v_strp_strp [3:0] $end
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$var wire 2 ) v_unip_strp [1:0] $end
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$scope module p2 $end
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$var wire 32 B PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var wire 32 C PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var wire 32 D PARAM [31:0] $end
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$upscope $end
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$scope module unnamedblk1 $end
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$var wire 32 9 b [31:0] $end
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$var wire 32 : b [31:0] $end
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$scope module unnamedblk2 $end
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$var wire 32 : a [31:0] $end
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$var wire 32 ; a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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@ -69,17 +70,18 @@ r0 3
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r0 5
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b00000000000000000000000000000000 7
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b00000000000000000000000000000000 8
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b00000000000000000000000000000000 9
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b000 9
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b00000000000000000000000000000000 :
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0;
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b00000000000000000000000000000000 ;
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0<
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0=
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0>
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0?
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0@
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0A
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b00000000000000000000000000000010 B
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b00000000000000000000000000000011 C
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0B
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b00000000000000000000000000000010 C
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b00000000000000000000000000000011 D
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#10
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b00000000000000000000000000000001 $
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b0000000000000000000000000000000100000000000000000000000011111110 %
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@ -98,11 +100,12 @@ r0.2 3
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r0.3 5
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b00000000000000000000000000000001 7
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b00000000000000000000000000000010 8
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b00000000000000000000000000000101 9
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b111 9
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b00000000000000000000000000000101 :
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1;
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b00000000000000000000000000000101 ;
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1<
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#15
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0;
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0<
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#20
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b00000000000000000000000000000010 $
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b0000000000000000000000000000001000000000000000000000000011111101 %
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@ -121,9 +124,10 @@ r0.4 3
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r0.6 5
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b00000000000000000000000000000010 7
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b00000000000000000000000000000100 8
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1;
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b110 9
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1<
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#25
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0;
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0<
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#30
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b00000000000000000000000000000011 $
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b0000000000000000000000000000001100000000000000000000000011111100 %
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@ -142,9 +146,10 @@ r0.6000000000000001 3
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r0.8999999999999999 5
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b00000000000000000000000000000011 7
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b00000000000000000000000000000110 8
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1;
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b101 9
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1<
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#35
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0;
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0<
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#40
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b00000000000000000000000000000100 $
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b0000000000000000000000000000010000000000000000000000000011111011 %
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@ -163,9 +168,10 @@ r0.8 3
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r1.2 5
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b00000000000000000000000000000100 7
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b00000000000000000000000000001000 8
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1;
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b100 9
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1<
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#45
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0;
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0<
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#50
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b00000000000000000000000000000101 $
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b0000000000000000000000000000010100000000000000000000000011111010 %
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@ -184,9 +190,10 @@ r1 3
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r1.5 5
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b00000000000000000000000000000101 7
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b00000000000000000000000000001010 8
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1;
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b011 9
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1<
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#55
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0;
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0<
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#60
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b00000000000000000000000000000110 $
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b0000000000000000000000000000011000000000000000000000000011111001 %
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@ -205,4 +212,5 @@ r1.2 3
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r1.8 5
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b00000000000000000000000000000110 7
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b00000000000000000000000000001100 8
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1;
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b010 9
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1<
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@ -59,6 +59,8 @@ module t (clk);
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typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t;
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enumed_t v_enumed;
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enumed_t v_enumed2;
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typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t;
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enumb_t v_enumb;
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p #(.PARAM(2)) p2 ();
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p #(.PARAM(3)) p3 ();
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@ -77,6 +79,7 @@ module t (clk);
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v_arr_real[1] <= v_arr_real[1] + 0.3;
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v_enumed <= v_enumed + 1;
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v_enumed2 <= v_enumed2 + 2;
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v_enumb <= v_enumb - 1;
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for (integer b=3; b<=4; b++) begin
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v_arru[b] <= ~v_arru[b];
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v_arru_strp[b] <= ~v_arru_strp[b];
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@ -1,5 +1,5 @@
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$date
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Sun Oct 21 21:56:13 2018
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Wed May 1 19:09:18 2019
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$end
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$version
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@ -38,21 +38,24 @@ $attrbegin misc 07 "" 1 $end
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$var logic 32 7 v_enumed $end
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$attrbegin misc 07 "" 1 $end
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$var logic 32 8 v_enumed2 $end
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$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
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$attrbegin misc 07 "" 2 $end
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$var logic 3 9 v_enumb $end
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$scope module unnamedblk1 $end
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$var integer 32 9 b $end
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$var integer 32 : b $end
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$scope module unnamedblk2 $end
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$var integer 32 : a $end
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$var integer 32 ; a $end
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$upscope $end
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$upscope $end
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$scope module p2 $end
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$var parameter 32 ; PARAM $end
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$var parameter 32 < PARAM $end
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$upscope $end
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$scope module p3 $end
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$var parameter 32 < PARAM $end
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$var parameter 32 = PARAM $end
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$upscope $end
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$upscope $end
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$scope module $unit $end
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$var bit 1 = global_bit $end
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$var bit 1 > global_bit $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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@ -81,14 +84,16 @@ r0 5
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b0000000000000000000000000000000000000000000000000000000011111111 6
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b00000000000000000000000000000000 7
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b00000000000000000000000000000000 8
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b00000000000000000000000000000000 9
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b000 9
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b00000000000000000000000000000000 :
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b00000000000000000000000000000010 ;
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b00000000000000000000000000000011 <
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1=
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b00000000000000000000000000000000 ;
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b00000000000000000000000000000010 <
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b00000000000000000000000000000011 =
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1>
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#10
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b00000000000000000000000000000101 ;
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b00000000000000000000000000000101 :
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b00000000000000000000000000000101 9
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b111 9
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b00000000000000000000000000000010 8
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b00000000000000000000000000000001 7
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b0000000000000000000000000000000100000000000000000000000011111110 6
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@ -128,14 +133,16 @@ r0.6 5
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b0000000000000000000000000000001000000000000000000000000011111101 6
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b00000000000000000000000000000010 7
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b00000000000000000000000000000100 8
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b00000000000000000000000000000101 9
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b110 9
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b00000000000000000000000000000101 :
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b00000000000000000000000000000101 ;
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#25
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0!
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#30
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1!
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b00000000000000000000000000000101 ;
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b00000000000000000000000000000101 :
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b00000000000000000000000000000101 9
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b101 9
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b00000000000000000000000000000110 8
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b00000000000000000000000000000011 7
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b0000000000000000000000000000001100000000000000000000000011111100 6
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@ -174,14 +181,16 @@ r1.2 5
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b0000000000000000000000000000010000000000000000000000000011111011 6
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b00000000000000000000000000000100 7
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b00000000000000000000000000001000 8
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b00000000000000000000000000000101 9
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b100 9
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b00000000000000000000000000000101 :
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b00000000000000000000000000000101 ;
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#45
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0!
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#50
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1!
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b00000000000000000000000000000101 ;
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b00000000000000000000000000000101 :
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b00000000000000000000000000000101 9
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b011 9
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b00000000000000000000000000001010 8
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b00000000000000000000000000000101 7
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b0000000000000000000000000000010100000000000000000000000011111010 6
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@ -220,5 +229,6 @@ r1.8 5
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b0000000000000000000000000000011000000000000000000000000011111001 6
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b00000000000000000000000000000110 7
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b00000000000000000000000000001100 8
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b00000000000000000000000000000101 9
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b010 9
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b00000000000000000000000000000101 :
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b00000000000000000000000000000101 ;
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@ -1,31 +1,32 @@
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$version Generated by VerilatedVcd $end
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$date Sun Oct 7 21:58:07 2018
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$date Wed May 1 19:09:21 2019
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 ; clk $end
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$var wire 1 < clk $end
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$scope module $unit $end
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$var wire 1 # global_bit $end
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$upscope $end
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$scope module t $end
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$var wire 1 ; clk $end
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$var wire 1 < clk $end
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$var wire 32 $ cyc [31:0] $end
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$var real 64 3 v_arr_real(0) $end
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$var real 64 5 v_arr_real(1) $end
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$var wire 2 * v_arrp [2:1] $end
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$var wire 4 + v_arrp_arrp [3:0] $end
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$var wire 4 , v_arrp_strp [3:0] $end
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$var wire 1 < v_arru(1) $end
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$var wire 1 = v_arru(2) $end
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$var wire 1 = v_arru(1) $end
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$var wire 1 > v_arru(2) $end
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$var wire 2 - v_arru_arrp(3) [2:1] $end
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$var wire 2 . v_arru_arrp(4) [2:1] $end
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$var wire 1 > v_arru_arru(3)(1) $end
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$var wire 1 ? v_arru_arru(3)(2) $end
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$var wire 1 @ v_arru_arru(4)(1) $end
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$var wire 1 A v_arru_arru(4)(2) $end
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$var wire 1 ? v_arru_arru(3)(1) $end
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$var wire 1 @ v_arru_arru(3)(2) $end
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$var wire 1 A v_arru_arru(4)(1) $end
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$var wire 1 B v_arru_arru(4)(2) $end
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$var wire 2 / v_arru_strp(3) [1:0] $end
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$var wire 2 0 v_arru_strp(4) [1:0] $end
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$var wire 3 9 v_enumb [2:0] $end
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$var wire 32 7 v_enumed [31:0] $end
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$var wire 32 8 v_enumed2 [31:0] $end
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$var real 64 1 v_real $end
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@ -34,15 +35,15 @@ $timescale 1ns $end
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$var wire 4 ( v_strp_strp [3:0] $end
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$var wire 2 ) v_unip_strp [1:0] $end
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$scope module p2 $end
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$var wire 32 B PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var wire 32 C PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var wire 32 D PARAM [31:0] $end
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$upscope $end
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$scope module unnamedblk1 $end
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$var wire 32 9 b [31:0] $end
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$var wire 32 : b [31:0] $end
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$scope module unnamedblk2 $end
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$var wire 32 : a [31:0] $end
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$var wire 32 ; a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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@ -69,17 +70,18 @@ r0 3
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r0 5
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b00000000000000000000000000000000 7
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b00000000000000000000000000000000 8
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b00000000000000000000000000000000 9
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b000 9
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b00000000000000000000000000000000 :
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0;
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b00000000000000000000000000000000 ;
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0<
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0=
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0>
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0?
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0@
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0A
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b00000000000000000000000000000010 B
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b00000000000000000000000000000011 C
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0B
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b00000000000000000000000000000010 C
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b00000000000000000000000000000011 D
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#10
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b00000000000000000000000000000001 $
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b0000000000000000000000000000000100000000000000000000000011111110 %
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@ -98,11 +100,12 @@ r0.2 3
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r0.3 5
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b00000000000000000000000000000001 7
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b00000000000000000000000000000010 8
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b00000000000000000000000000000101 9
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b111 9
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b00000000000000000000000000000101 :
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1;
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b00000000000000000000000000000101 ;
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1<
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#15
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0;
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0<
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#20
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b00000000000000000000000000000010 $
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b0000000000000000000000000000001000000000000000000000000011111101 %
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@ -121,9 +124,10 @@ r0.4 3
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r0.6 5
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b00000000000000000000000000000010 7
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b00000000000000000000000000000100 8
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1;
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b110 9
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1<
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#25
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0;
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0<
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#30
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b00000000000000000000000000000011 $
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b0000000000000000000000000000001100000000000000000000000011111100 %
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@ -142,9 +146,10 @@ r0.6000000000000001 3
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r0.8999999999999999 5
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b00000000000000000000000000000011 7
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b00000000000000000000000000000110 8
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1;
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b101 9
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1<
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#35
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0;
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0<
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#40
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b00000000000000000000000000000100 $
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b0000000000000000000000000000010000000000000000000000000011111011 %
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@ -163,9 +168,10 @@ r0.8 3
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r1.2 5
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b00000000000000000000000000000100 7
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b00000000000000000000000000001000 8
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1;
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b100 9
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1<
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#45
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0;
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0<
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#50
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b00000000000000000000000000000101 $
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b0000000000000000000000000000010100000000000000000000000011111010 %
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@ -184,9 +190,10 @@ r1 3
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r1.5 5
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b00000000000000000000000000000101 7
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b00000000000000000000000000001010 8
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1;
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b011 9
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1<
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#55
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0;
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0<
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#60
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b00000000000000000000000000000110 $
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b0000000000000000000000000000011000000000000000000000000011111001 %
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@ -205,4 +212,5 @@ r1.2 3
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||||
r1.8 5
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b00000000000000000000000000000110 7
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b00000000000000000000000000001100 8
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1;
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b010 9
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1<
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|
@ -1,5 +1,5 @@
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$date
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Sun Oct 21 21:56:26 2018
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Wed May 1 19:09:23 2019
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||||
|
||||
$end
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$version
|
||||
@ -38,21 +38,24 @@ $attrbegin misc 07 "" 1 $end
|
||||
$var logic 32 7 v_enumed $end
|
||||
$attrbegin misc 07 "" 1 $end
|
||||
$var logic 32 8 v_enumed2 $end
|
||||
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
|
||||
$attrbegin misc 07 "" 2 $end
|
||||
$var logic 3 9 v_enumb $end
|
||||
$scope module unnamedblk1 $end
|
||||
$var integer 32 9 b $end
|
||||
$var integer 32 : b $end
|
||||
$scope module unnamedblk2 $end
|
||||
$var integer 32 : a $end
|
||||
$var integer 32 ; a $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module p2 $end
|
||||
$var parameter 32 ; PARAM $end
|
||||
$var parameter 32 < PARAM $end
|
||||
$upscope $end
|
||||
$scope module p3 $end
|
||||
$var parameter 32 < PARAM $end
|
||||
$var parameter 32 = PARAM $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module $unit $end
|
||||
$var bit 1 = global_bit $end
|
||||
$var bit 1 > global_bit $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
@ -81,14 +84,16 @@ r0 5
|
||||
b0000000000000000000000000000000000000000000000000000000011111111 6
|
||||
b00000000000000000000000000000000 7
|
||||
b00000000000000000000000000000000 8
|
||||
b00000000000000000000000000000000 9
|
||||
b000 9
|
||||
b00000000000000000000000000000000 :
|
||||
b00000000000000000000000000000010 ;
|
||||
b00000000000000000000000000000011 <
|
||||
1=
|
||||
b00000000000000000000000000000000 ;
|
||||
b00000000000000000000000000000010 <
|
||||
b00000000000000000000000000000011 =
|
||||
1>
|
||||
#10
|
||||
b00000000000000000000000000000101 ;
|
||||
b00000000000000000000000000000101 :
|
||||
b00000000000000000000000000000101 9
|
||||
b111 9
|
||||
b00000000000000000000000000000010 8
|
||||
b00000000000000000000000000000001 7
|
||||
b0000000000000000000000000000000100000000000000000000000011111110 6
|
||||
@ -128,14 +133,16 @@ r0.6 5
|
||||
b0000000000000000000000000000001000000000000000000000000011111101 6
|
||||
b00000000000000000000000000000010 7
|
||||
b00000000000000000000000000000100 8
|
||||
b00000000000000000000000000000101 9
|
||||
b110 9
|
||||
b00000000000000000000000000000101 :
|
||||
b00000000000000000000000000000101 ;
|
||||
#25
|
||||
0!
|
||||
#30
|
||||
1!
|
||||
b00000000000000000000000000000101 ;
|
||||
b00000000000000000000000000000101 :
|
||||
b00000000000000000000000000000101 9
|
||||
b101 9
|
||||
b00000000000000000000000000000110 8
|
||||
b00000000000000000000000000000011 7
|
||||
b0000000000000000000000000000001100000000000000000000000011111100 6
|
||||
@ -174,14 +181,16 @@ r1.2 5
|
||||
b0000000000000000000000000000010000000000000000000000000011111011 6
|
||||
b00000000000000000000000000000100 7
|
||||
b00000000000000000000000000001000 8
|
||||
b00000000000000000000000000000101 9
|
||||
b100 9
|
||||
b00000000000000000000000000000101 :
|
||||
b00000000000000000000000000000101 ;
|
||||
#45
|
||||
0!
|
||||
#50
|
||||
1!
|
||||
b00000000000000000000000000000101 ;
|
||||
b00000000000000000000000000000101 :
|
||||
b00000000000000000000000000000101 9
|
||||
b011 9
|
||||
b00000000000000000000000000001010 8
|
||||
b00000000000000000000000000000101 7
|
||||
b0000000000000000000000000000010100000000000000000000000011111010 6
|
||||
@ -220,5 +229,6 @@ r1.8 5
|
||||
b0000000000000000000000000000011000000000000000000000000011111001 6
|
||||
b00000000000000000000000000000110 7
|
||||
b00000000000000000000000000001100 8
|
||||
b00000000000000000000000000000101 9
|
||||
b010 9
|
||||
b00000000000000000000000000000101 :
|
||||
b00000000000000000000000000000101 ;
|
||||
|
@ -1,36 +1,37 @@
|
||||
$version Generated by VerilatedVcd $end
|
||||
$date Sun Oct 7 21:58:08 2018
|
||||
$date Wed May 1 19:09:26 2019
|
||||
$end
|
||||
$timescale 1ns $end
|
||||
|
||||
$scope module top $end
|
||||
$var wire 1 F clk $end
|
||||
$var wire 1 G clk $end
|
||||
$scope module $unit $end
|
||||
$var wire 1 # global_bit $end
|
||||
$upscope $end
|
||||
$scope module t $end
|
||||
$var wire 1 F clk $end
|
||||
$var wire 1 G clk $end
|
||||
$var wire 32 $ cyc [31:0] $end
|
||||
$var real 64 > v_arr_real(0) $end
|
||||
$var real 64 @ v_arr_real(1) $end
|
||||
$var wire 2 / v_arrp [2:1] $end
|
||||
$var wire 2 0 v_arrp_arrp(3) [1:0] $end
|
||||
$var wire 2 1 v_arrp_arrp(4) [1:0] $end
|
||||
$var wire 1 G v_arru(1) $end
|
||||
$var wire 1 H v_arru(2) $end
|
||||
$var wire 1 H v_arru(1) $end
|
||||
$var wire 1 I v_arru(2) $end
|
||||
$var wire 2 6 v_arru_arrp(3) [2:1] $end
|
||||
$var wire 2 7 v_arru_arrp(4) [2:1] $end
|
||||
$var wire 1 I v_arru_arru(3)(1) $end
|
||||
$var wire 1 J v_arru_arru(3)(2) $end
|
||||
$var wire 1 K v_arru_arru(4)(1) $end
|
||||
$var wire 1 L v_arru_arru(4)(2) $end
|
||||
$var wire 1 J v_arru_arru(3)(1) $end
|
||||
$var wire 1 K v_arru_arru(3)(2) $end
|
||||
$var wire 1 L v_arru_arru(4)(1) $end
|
||||
$var wire 1 M v_arru_arru(4)(2) $end
|
||||
$var wire 3 D v_enumb [2:0] $end
|
||||
$var wire 32 B v_enumed [31:0] $end
|
||||
$var wire 32 C v_enumed2 [31:0] $end
|
||||
$var real 64 < v_real $end
|
||||
$scope module unnamedblk1 $end
|
||||
$var wire 32 D b [31:0] $end
|
||||
$var wire 32 E b [31:0] $end
|
||||
$scope module unnamedblk2 $end
|
||||
$var wire 32 E a [31:0] $end
|
||||
$var wire 32 F a [31:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module v_arrp_strp(3) $end
|
||||
@ -115,15 +116,16 @@ r0 >
|
||||
r0 @
|
||||
b00000000000000000000000000000000 B
|
||||
b00000000000000000000000000000000 C
|
||||
b00000000000000000000000000000000 D
|
||||
b000 D
|
||||
b00000000000000000000000000000000 E
|
||||
0F
|
||||
b00000000000000000000000000000000 F
|
||||
0G
|
||||
0H
|
||||
0I
|
||||
0J
|
||||
0K
|
||||
0L
|
||||
0M
|
||||
#10
|
||||
b00000000000000000000000000000001 $
|
||||
b00000000000000000000000011111110 %
|
||||
@ -154,11 +156,12 @@ r0.2 >
|
||||
r0.3 @
|
||||
b00000000000000000000000000000001 B
|
||||
b00000000000000000000000000000010 C
|
||||
b00000000000000000000000000000101 D
|
||||
b111 D
|
||||
b00000000000000000000000000000101 E
|
||||
1F
|
||||
b00000000000000000000000000000101 F
|
||||
1G
|
||||
#15
|
||||
0F
|
||||
0G
|
||||
#20
|
||||
b00000000000000000000000000000010 $
|
||||
b00000000000000000000000011111101 %
|
||||
@ -189,9 +192,10 @@ r0.4 >
|
||||
r0.6 @
|
||||
b00000000000000000000000000000010 B
|
||||
b00000000000000000000000000000100 C
|
||||
1F
|
||||
b110 D
|
||||
1G
|
||||
#25
|
||||
0F
|
||||
0G
|
||||
#30
|
||||
b00000000000000000000000000000011 $
|
||||
b00000000000000000000000011111100 %
|
||||
@ -222,9 +226,10 @@ r0.6000000000000001 >
|
||||
r0.8999999999999999 @
|
||||
b00000000000000000000000000000011 B
|
||||
b00000000000000000000000000000110 C
|
||||
1F
|
||||
b101 D
|
||||
1G
|
||||
#35
|
||||
0F
|
||||
0G
|
||||
#40
|
||||
b00000000000000000000000000000100 $
|
||||
b00000000000000000000000011111011 %
|
||||
@ -255,9 +260,10 @@ r0.8 >
|
||||
r1.2 @
|
||||
b00000000000000000000000000000100 B
|
||||
b00000000000000000000000000001000 C
|
||||
1F
|
||||
b100 D
|
||||
1G
|
||||
#45
|
||||
0F
|
||||
0G
|
||||
#50
|
||||
b00000000000000000000000000000101 $
|
||||
b00000000000000000000000011111010 %
|
||||
@ -288,9 +294,10 @@ r1 >
|
||||
r1.5 @
|
||||
b00000000000000000000000000000101 B
|
||||
b00000000000000000000000000001010 C
|
||||
1F
|
||||
b011 D
|
||||
1G
|
||||
#55
|
||||
0F
|
||||
0G
|
||||
#60
|
||||
b00000000000000000000000000000110 $
|
||||
b00000000000000000000000011111001 %
|
||||
@ -321,4 +328,5 @@ r1.2 >
|
||||
r1.8 @
|
||||
b00000000000000000000000000000110 B
|
||||
b00000000000000000000000000001100 C
|
||||
1F
|
||||
b010 D
|
||||
1G
|
||||
|
@ -1,5 +1,5 @@
|
||||
$date
|
||||
Sun Oct 21 21:56:37 2018
|
||||
Wed May 1 19:09:29 2019
|
||||
|
||||
$end
|
||||
$version
|
||||
@ -78,15 +78,18 @@ $attrbegin misc 07 "" 1 $end
|
||||
$var logic 32 C v_enumed $end
|
||||
$attrbegin misc 07 "" 1 $end
|
||||
$var logic 32 D v_enumed2 $end
|
||||
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
|
||||
$attrbegin misc 07 "" 2 $end
|
||||
$var logic 3 E v_enumb $end
|
||||
$scope module unnamedblk1 $end
|
||||
$var integer 32 E b $end
|
||||
$var integer 32 F b $end
|
||||
$scope module unnamedblk2 $end
|
||||
$var integer 32 F a $end
|
||||
$var integer 32 G a $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module $unit $end
|
||||
$var bit 1 G global_bit $end
|
||||
$var bit 1 H global_bit $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
@ -127,12 +130,14 @@ b00000000000000000000000011111111 A
|
||||
b00000000000000000000000000000000 B
|
||||
b00000000000000000000000000000000 C
|
||||
b00000000000000000000000000000000 D
|
||||
b00000000000000000000000000000000 E
|
||||
b000 E
|
||||
b00000000000000000000000000000000 F
|
||||
1G
|
||||
b00000000000000000000000000000000 G
|
||||
1H
|
||||
#10
|
||||
b00000000000000000000000000000101 G
|
||||
b00000000000000000000000000000101 F
|
||||
b00000000000000000000000000000101 E
|
||||
b111 E
|
||||
b00000000000000000000000000000010 D
|
||||
b00000000000000000000000000000001 C
|
||||
b00000000000000000000000000000001 B
|
||||
@ -196,14 +201,16 @@ b00000000000000000000000011111101 A
|
||||
b00000000000000000000000000000010 B
|
||||
b00000000000000000000000000000010 C
|
||||
b00000000000000000000000000000100 D
|
||||
b00000000000000000000000000000101 E
|
||||
b110 E
|
||||
b00000000000000000000000000000101 F
|
||||
b00000000000000000000000000000101 G
|
||||
#25
|
||||
0!
|
||||
#30
|
||||
1!
|
||||
b00000000000000000000000000000101 G
|
||||
b00000000000000000000000000000101 F
|
||||
b00000000000000000000000000000101 E
|
||||
b101 E
|
||||
b00000000000000000000000000000110 D
|
||||
b00000000000000000000000000000011 C
|
||||
b00000000000000000000000000000011 B
|
||||
@ -266,14 +273,16 @@ b00000000000000000000000011111011 A
|
||||
b00000000000000000000000000000100 B
|
||||
b00000000000000000000000000000100 C
|
||||
b00000000000000000000000000001000 D
|
||||
b00000000000000000000000000000101 E
|
||||
b100 E
|
||||
b00000000000000000000000000000101 F
|
||||
b00000000000000000000000000000101 G
|
||||
#45
|
||||
0!
|
||||
#50
|
||||
1!
|
||||
b00000000000000000000000000000101 G
|
||||
b00000000000000000000000000000101 F
|
||||
b00000000000000000000000000000101 E
|
||||
b011 E
|
||||
b00000000000000000000000000001010 D
|
||||
b00000000000000000000000000000101 C
|
||||
b00000000000000000000000000000101 B
|
||||
@ -336,5 +345,6 @@ b00000000000000000000000011111001 A
|
||||
b00000000000000000000000000000110 B
|
||||
b00000000000000000000000000000110 C
|
||||
b00000000000000000000000000001100 D
|
||||
b00000000000000000000000000000101 E
|
||||
b010 E
|
||||
b00000000000000000000000000000101 F
|
||||
b00000000000000000000000000000101 G
|
||||
|
Loading…
Reference in New Issue
Block a user