39 lines
1.4 KiB
Markdown
39 lines
1.4 KiB
Markdown
# Collection of SystemVerilog simple RV32I CPU cores
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## Table of contents
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- [Core list](#core-list)
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- [Directory structure](#directory-structure)
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- [Requirements](#requirements)
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- [Build](#build)
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- [Tests](#tests)
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- [Benchmark](#benchmark)
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## Core list
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- Single cycle processor
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- 5-Stage pipelined processor with hazard detection
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## Directory structure
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.
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├── fw # Firmware
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│ ├── sandbox # C/Assembly sandbox firmware source
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│ └── test # Assembly programs used for testbenchs
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├── rtl # RTL Modules
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└── test # SystemVerilog testbenchs
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## Requirements
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- SystemVerilog simulator
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- CMake
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- 32-bit GNU RISC-V toolchain
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If your package manager does not provide the RISC-V GNU toolchain you can compile it from their [main repository](https://github.com/riscv-collab/riscv-gnu-toolchain) or for Windows you can download the [xPack pre-compiled binaries](https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases).
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## Build
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To build the firmware that will be loaded in the instruction memory execute CMake in the `fw` directory specifying the RISC-V toolchain and build the recipe based in your selected generator (`make` in the following example).
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```
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cmake -DCMAKE_TOOLCHAIN_FILE=./cmake/toolchain.cmake -Bbuild
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make -Cbuild
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```
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## Tests
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(TODO)
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## Benchmark
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(TODO) |