RVSCC/README.md

Collection of SystemVerilog simple RV32I CPU cores

Table of contents

• Core list
• Directory structure
• Requirements
• Build
• Tests
• Benchmark

Core list

• Single cycle processor
• 5-Stage pipelined processor with hazard detection

Directory structure

.
├── fw                   # Firmware
│   ├── sandbox          # C/Assembly sandbox firmware source
│   └── test             # Assembly programs used for testbenchs
├── rtl                  # RTL Modules
└── test                 # SystemVerilog testbenchs

Requirements

• SystemVerilog simulator
• CMake
• 32-bit GNU RISC-V toolchain

If your package manager does not provide the RISC-V GNU toolchain you can compile it from their main repository or for Windows you can download the xPack pre-compiled binaries.

Build

To build the firmware that will be loaded in the instruction memory execute CMake in the fw directory specifying the RISC-V toolchain and build the recipe based in your selected generator (make in the following example).

cmake -DCMAKE_TOOLCHAIN_FILE=./cmake/toolchain.cmake -Bbuild
make -Cbuild

Tests

(TODO)

Benchmark

(TODO)