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102 lines
2.6 KiB
Systemverilog
102 lines
2.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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function int f_no_no ();
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int st = 2; st++; return st;
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endfunction
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function int f_no_st ();
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static int st = 2; st++; return st;
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endfunction
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function int f_no_au ();
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automatic int au = 2; au++; return au;
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endfunction
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function static int f_st_no ();
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int st = 2; st++; return st;
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endfunction
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function static int f_st_st ();
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static int st = 2; st++; return st;
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endfunction
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function static int f_st_au ();
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automatic int au = 2; au++; return au;
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endfunction
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function automatic int f_au_no ();
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int au = 2; au++; return au;
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endfunction
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function automatic int f_au_st ();
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static int st = 2; st++; return st;
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endfunction
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function automatic int f_au_au ();
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automatic int au = 2; au++; return au;
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endfunction
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int v;
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initial begin
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v = f_no_no(); `checkh(v, 3);
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v = f_no_no(); `checkh(v, 4);
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v = f_no_st(); `checkh(v, 3);
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v = f_no_st(); `checkh(v, 4);
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v = f_no_au(); `checkh(v, 3);
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v = f_no_au(); `checkh(v, 3);
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//
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v = f_st_no(); `checkh(v, 3);
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v = f_st_no(); `checkh(v, 4);
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v = f_st_st(); `checkh(v, 3);
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v = f_st_st(); `checkh(v, 4);
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v = f_st_au(); `checkh(v, 3);
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v = f_st_au(); `checkh(v, 3);
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//
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v = f_au_no(); `checkh(v, 3);
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v = f_au_no(); `checkh(v, 3);
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v = f_au_st(); `checkh(v, 3);
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v = f_au_st(); `checkh(v, 4);
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v = f_au_au(); `checkh(v, 3);
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v = f_au_au(); `checkh(v, 3);
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//
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end
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int cyc = 0;
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always @ (posedge clk) begin
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int ist1;
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static int ist2;
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automatic int iau3;
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cyc <= cyc + 1;
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if (cyc == 0) begin
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ist1 = 10;
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ist2 = 20;
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iau3 = 30;
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v = ist1; `checkh(v, 10);
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v = ist2; `checkh(v, 20);
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v = iau3; `checkh(v, 30);
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++ist1;
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++ist2;
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++iau3;
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end
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else if (cyc == 1) begin
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v = ist1; `checkh(v, 11);
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v = ist2; `checkh(v, 21);
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//TODO v = iau3; `checkh(v, 0);
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end
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else if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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