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Tests: Better static tests
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9
test_regress/t/t_class_static.out
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9
test_regress/t/t_class_static.out
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%Error-UNSUPPORTED: t/t_class_static.v:12:15: Unsupported: 'static' class members
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: ... In instance t
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12 | static int c_st = 2;
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| ^~~~
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%Error-UNSUPPORTED: t/t_class_static.v:25:18: Unsupported: 'static' function/task variables
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: ... In instance t
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25 | static int st = 2; st++; return st;
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| ^~
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%Error: Exiting due to
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23
test_regress/t/t_class_static.pl
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23
test_regress/t/t_class_static.pl
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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expect_filename => $Self->{golden_filename},
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fails => $Self->{vlt_all} # Verilator unsupported, bug546
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);
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#execute(
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# check_finished => 1,
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# );
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ok(1);
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1;
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71
test_regress/t/t_class_static.v
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71
test_regress/t/t_class_static.v
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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class Cls;
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int c_no = 2;
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//automatic int c_au = 2; // automatic not a legal keyword here
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static int c_st = 2;
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function int f_c_no ();
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++c_no; return c_no;
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endfunction
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function int f_c_st ();
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++c_st; return c_st;
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endfunction
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function int f_no_no ();
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int au = 2; au++; return au;
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endfunction
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function int f_no_st ();
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static int st = 2; st++; return st;
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endfunction
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function int f_no_au ();
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automatic int au = 2; au++; return au;
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endfunction
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endclass
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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Cls a = new;
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Cls b = new;
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int v;
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initial begin
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v = a.f_c_no(); `checkh(v,3);
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v = a.f_c_no(); `checkh(v, 4);
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v = b.f_c_no(); `checkh(v, 3);
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v = b.f_c_no(); `checkh(v, 4);
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v = a.f_c_st(); `checkh(v,3);
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v = a.f_c_st(); `checkh(v, 4);
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v = b.f_c_st(); `checkh(v, 5);
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v = b.f_c_st(); `checkh(v, 6);
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//
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v = a.f_no_no(); `checkh(v, 3);
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v = a.f_no_no(); `checkh(v, 3);
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v = b.f_no_no(); `checkh(v, 3);
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v = b.f_no_no(); `checkh(v, 3);
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v = a.f_no_st(); `checkh(v, 3);
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v = a.f_no_st(); `checkh(v, 4);
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v = b.f_no_st(); `checkh(v, 5);
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v = b.f_no_st(); `checkh(v, 6);
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v = a.f_no_au(); `checkh(v, 3);
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v = a.f_no_au(); `checkh(v, 3);
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v = b.f_no_au(); `checkh(v, 3);
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v = b.f_no_au(); `checkh(v, 3);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -43,27 +43,29 @@ module t (/*AUTOARG*/
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automatic int au = 2; au++; return au;
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endfunction
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int v;
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initial begin
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`checkh(f_no_no(), 3);
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`checkh(f_no_no(), 4);
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`checkh(f_no_st(), 3);
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`checkh(f_no_st(), 4);
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`checkh(f_no_au(), 3);
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`checkh(f_no_au(), 3);
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v = f_no_no(); `checkh(v, 3);
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v = f_no_no(); `checkh(v, 4);
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v = f_no_st(); `checkh(v, 3);
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v = f_no_st(); `checkh(v, 4);
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v = f_no_au(); `checkh(v, 3);
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v = f_no_au(); `checkh(v, 3);
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//
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`checkh(f_st_no(), 3);
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`checkh(f_st_no(), 4);
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`checkh(f_st_st(), 3);
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`checkh(f_st_st(), 4);
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`checkh(f_st_au(), 3);
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`checkh(f_st_au(), 3);
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v = f_st_no(); `checkh(v, 3);
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v = f_st_no(); `checkh(v, 4);
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v = f_st_st(); `checkh(v, 3);
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v = f_st_st(); `checkh(v, 4);
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v = f_st_au(); `checkh(v, 3);
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v = f_st_au(); `checkh(v, 3);
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//
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`checkh(f_au_no(), 3);
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`checkh(f_au_no(), 3);
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`checkh(f_au_st(), 3);
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`checkh(f_au_st(), 4);
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`checkh(f_au_au(), 3);
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`checkh(f_au_au(), 3);
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v = f_au_no(); `checkh(v, 3);
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v = f_au_no(); `checkh(v, 3);
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v = f_au_st(); `checkh(v, 3);
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v = f_au_st(); `checkh(v, 4);
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v = f_au_au(); `checkh(v, 3);
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v = f_au_au(); `checkh(v, 3);
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//
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end
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@ -78,17 +80,17 @@ module t (/*AUTOARG*/
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ist1 = 10;
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ist2 = 20;
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iau3 = 30;
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`checkh(ist1, 10);
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`checkh(ist2, 20);
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`checkh(iau3, 30);
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v = ist1; `checkh(v, 10);
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v = ist2; `checkh(v, 20);
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v = iau3; `checkh(v, 30);
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++ist1;
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++ist2;
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++iau3;
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end
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else if (cyc == 1) begin
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`checkh(ist1, 11);
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`checkh(ist2, 21);
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`checkh(iau3, 0);
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v = ist1; `checkh(v, 11);
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v = ist2; `checkh(v, 21);
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//TODO v = iau3; `checkh(v, 0);
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end
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else if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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5
test_regress/t/t_var_static_param.out
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5
test_regress/t/t_var_static_param.out
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%Error-UNSUPPORTED: t/t_var_static_param.v:32:18: Unsupported: 'static' function/task variables
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: ... In instance t.subb
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32 | static int st = 2; st += P; return st;
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| ^~
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%Error: Exiting due to
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23
test_regress/t/t_var_static_param.pl
Executable file
23
test_regress/t/t_var_static_param.pl
Executable file
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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expect_filename => $Self->{golden_filename},
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fails => $Self->{vlt_all} # Verilator unsupported, bug546
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);
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#execute(
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# check_finished => 1,
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# );
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ok(1);
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1;
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34
test_regress/t/t_var_static_param.v
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34
test_regress/t/t_var_static_param.v
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
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module t (/*AUTOARG*/);
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sub #(.P(1)) suba ();
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sub #(.P(10)) subb ();
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int v;
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initial begin
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v = suba.f_no_st(); `checkh(v, 3);
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v = suba.f_no_st(); `checkh(v, 4);
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v = subb.f_no_st(); `checkh(v, 'hc);
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v = subb.f_no_st(); `checkh(v, 'h16);
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v = suba.f_no_st(); `checkh(v, 5);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub;
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parameter P = 1;
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function int f_no_st ();
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// This static is unique within each parameterized module
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static int st = 2; st += P; return st;
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endfunction
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endmodule
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