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70 lines
2.0 KiB
Verilog
70 lines
2.0 KiB
Verilog
// DESCRIPTION::Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Wilson Snyder.
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module t;
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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typedef enum logic [1:0]
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{ ZERO = 2'd0,
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ONE = 2'd1,
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TWO = 2'd2,
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THREE = 2'd3,
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XXX = 2'dx
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} num_t;
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function automatic logic is_odd;
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input en;
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input num_t number;
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case (en)
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1'b1: begin
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unique if (number inside {ONE, THREE})
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is_odd = 1'b1;
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else if (number inside {ZERO, TWO})
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is_odd = 1'b0;
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else
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is_odd = 1'bx;
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end
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1'b0: is_odd = 1'bx;
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default: is_odd = 1'bx;
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endcase
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endfunction
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initial begin
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`checkh ((4'd4 inside {4'd1,4'd5}), 1'b0);
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`checkh ((4'd4 inside {4'd1,4'd4}), 1'b1);
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//
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`checkh ((4'b1011 inside {4'b1001}), 1'b0);
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`checkh ((4'b1011 inside {4'b1xx1}), 1'b1); // Uses ==?
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`checkh ((4'b1001 inside {4'b1xx1}), 1'b1); // Uses ==?
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`checkh ((4'b1001 inside {4'b1??1}), 1'b1);
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`ifndef VERILATOR
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`checkh ((4'b1z11 inside {4'b11?1, 4'b1011}),1'bx);
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`endif
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// Range
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`checkh ((4'd4 inside {[4'd5:4'd3], [4'd10:4'd8]}), 1'b0); // If left of colon < never matches
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`checkh ((4'd3 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
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`checkh ((4'd4 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
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`checkh ((4'd5 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
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//
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// Unsupported $ bound
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//
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// Unsupported if unpacked array, elements tranversed
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//int unpackedarray [$] = '{8,9};
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//( expr inside {2, 3, unpackedarray}) // { 2,3,8,9}
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//
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`checkh (is_odd(1'b1, ZERO), 1'd0);
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`checkh (is_odd(1'b1, ONE), 1'd1);
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`checkh (is_odd(1'b1, TWO), 1'd0);
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`checkh (is_odd(1'b1, THREE),1'd1);
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`ifndef VERILATOR
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`checkh (is_odd(1'b1, XXX), 1'dx);
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`endif
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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