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Support inside expressions.
This commit is contained in:
Wilson Snyder
parent
91159da30d
commit
4968a2abc5
2
Changes
2
Changes
@ -18,6 +18,8 @@ indicates the contributor was also the author of the fix; Thanks!
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*** Support $left, $right and related functions, bug448. [Iztok Jeras]
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*** Support inside expressions.
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*** Define SYSTEMVERILOG, SV_COV_START and other IEEE mandated predefines.
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**** Fix pin width mismatch error, bug595. [Alex Solomatnikov]
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@ -2558,6 +2558,11 @@ the disable statement itself is inside. This was commonly used to provide
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loop break and continue functionality before SystemVerilog added the break
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and continue keywords.
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=item inside
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Inside expressions may not include unpacked array traversal or $ as an
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upper bound. Case inside and case matches are also unsupported.
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=item priority if, unique if
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Priority and unique if's are treated as normal ifs and not asserted to be
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@ -2552,6 +2552,33 @@ struct AstFinal : public AstNode {
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AstNode* bodysp() const { return op1p()->castNode(); } // op1 = Expressions to evaluate
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};
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struct AstInside : public AstNodeMath {
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AstInside(FileLine* fl, AstNode* exprp, AstNode* itemsp)
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: AstNodeMath(fl) {
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addOp1p(exprp); addOp2p(itemsp);
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dtypeSetLogicBool();
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}
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ASTNODE_NODE_FUNCS(Inside, INSIDE)
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AstNode* exprp() const { return op1p()->castNode(); } // op1 = LHS expression to compare with
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AstNode* itemsp() const { return op2p()->castNode(); } // op2 = RHS, possibly a list of expr or AstInsideRange
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virtual string emitVerilog() { return "%l inside { %r }"; }
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virtual string emitC() { V3ERROR_NA; return ""; }
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virtual bool cleanOut() { return false; } // NA
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};
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struct AstInsideRange : public AstNodeMath {
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AstInsideRange(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
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: AstNodeMath(fl) {
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addOp1p(lhsp); addOp2p(rhsp);
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}
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ASTNODE_NODE_FUNCS(InsideRange, INSIDERANGE)
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AstNode* lhsp() const { return op1p()->castNode(); } // op1 = LHS
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AstNode* rhsp() const { return op2p()->castNode(); } // op2 = RHS
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virtual string emitVerilog() { return "[%l:%r]"; }
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virtual string emitC() { V3ERROR_NA; return ""; }
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virtual bool cleanOut() { return false; } // NA
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};
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struct AstInitArray : public AstNode {
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// Set a var to a large list of values
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// The values must be in sorted order, and not exceed the size of the var's array.
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@ -996,6 +996,58 @@ private:
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// Should be correct by construction, so we'll just loop through all types
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nodep->iterateChildren(*this, vup);
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}
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virtual void visit(AstInside* nodep, AstNUser* vup) {
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nodep->exprp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
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for (AstNode* nextip, *itemp = nodep->itemsp(); itemp; itemp=nextip) {
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nextip = itemp->nextp(); // Prelim may cause the node to get replaced
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itemp->iterate(*this,WidthVP(ANYSIZE,0,PRELIM).p()); itemp=NULL;
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}
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// Take width as maximum across all items
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int width = nodep->exprp()->width();
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int mwidth = nodep->exprp()->widthMin();
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for (AstNode* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()) {
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width = max(width,itemp->width());
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mwidth = max(mwidth,itemp->widthMin());
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}
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// Apply width
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nodep->exprp()->iterateAndNext(*this,WidthVP(width,mwidth,FINAL).p());
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for (AstNode* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()) {
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widthCheck(nodep,"Inside Item",itemp,width,mwidth);
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}
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widthCheck(nodep,"Inside expression",nodep->exprp(),width,mwidth);
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nodep->dtypeSetLogicBool();
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if (debug()>=9) nodep->dumpTree(cout,"-inside-in: ");
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// Now rip out the inside and replace with simple math
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AstNode* newp = NULL;
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for (AstNode* nextip, *itemp = nodep->itemsp(); itemp; itemp=nextip) {
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nextip = itemp->nextp(); // Will be unlinking
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AstNode* inewp;
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if (AstInsideRange* irangep = itemp->castInsideRange()) {
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inewp = new AstAnd(itemp->fileline(),
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new AstGte(itemp->fileline(),
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nodep->exprp()->cloneTree(true),
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irangep->lhsp()->unlinkFrBack()),
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new AstLte(itemp->fileline(),
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nodep->exprp()->cloneTree(true),
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irangep->rhsp()->unlinkFrBack()));
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} else {
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inewp = new AstEqWild(itemp->fileline(),
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nodep->exprp()->cloneTree(true),
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itemp->unlinkFrBack());
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}
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if (newp) newp = new AstOr(nodep->fileline(), newp, inewp);
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else newp = inewp;
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}
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if (!newp) newp = new AstConst(nodep->fileline(), AstConst::LogicFalse());
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if (debug()>=9) newp->dumpTree(cout,"-inside-out: ");
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nodep->replaceWith(newp); pushDeletep(nodep); nodep=NULL;
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}
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virtual void visit(AstInsideRange* nodep, AstNUser* vup) {
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// Just do each side; AstInside will rip these nodes out later
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nodep->lhsp()->iterateAndNext(*this,vup);
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nodep->rhsp()->iterateAndNext(*this,vup);
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nodep->dtypeFrom(nodep->lhsp());
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}
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virtual void visit(AstNodeClassDType* nodep, AstNUser* vup) {
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if (nodep->didWidthAndSet()) return; // This node is a dtype & not both PRELIMed+FINALed
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@ -424,6 +424,7 @@ word [a-zA-Z0-9_]+
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"final" { FL; return yFINAL; }
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"iff" { FL; return yIFF; }
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"import" { FL; return yIMPORT; }
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"inside" { FL; return yINSIDE; }
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"int" { FL; return yINT; }
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"logic" { FL; return yLOGIC; }
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"longint" { FL; return yLONGINT; }
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@ -469,7 +470,6 @@ word [a-zA-Z0-9_]+
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"forkjoin" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
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"ignore_bins" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
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"illegal_bins" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
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"inside" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
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"interface" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
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"intersect" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
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"join_any" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
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@ -332,6 +332,7 @@ class AstSenTree;
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%token<fl> yINITIAL "initial"
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%token<fl> yINOUT "inout"
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%token<fl> yINPUT "input"
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%token<fl> yINSIDE "inside"
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%token<fl> yINT "int"
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%token<fl> yINTEGER "integer"
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%token<fl> yLOCALPARAM "localparam"
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@ -557,7 +558,7 @@ class AstSenTree;
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// PSL op precedence
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%right yP_MINUSGT yP_LOGIFF
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%right yP_ORMINUSGT yP_OREQGT
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%left<fl> prPSLCLK
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%left<fl> prPSLCLK
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// Verilog op precedence
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%right '?' ':'
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@ -567,7 +568,7 @@ class AstSenTree;
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%left '^' yP_XNOR
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%left '&' yP_NAND
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%left yP_EQUAL yP_NOTEQUAL yP_CASEEQUAL yP_CASENOTEQUAL yP_WILDEQUAL yP_WILDNOTEQUAL
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%left '>' '<' yP_GTE yP_LTE yP_LTE__IGNORE
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%left '>' '<' yP_GTE yP_LTE yP_LTE__IGNORE yINSIDE
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%left yP_SLEFT yP_SRIGHT yP_SSRIGHT
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%left '+' '-'
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%left '*' '/' '%'
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@ -2245,6 +2246,20 @@ case_itemList<caseitemp>: // IEEE: { case_item + ... }
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| case_itemList yDEFAULT ':' stmtBlock { $$ = $1;$1->addNext(new AstCaseItem($3,NULL,$4)); }
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;
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open_range_list<nodep>: // ==IEEE: open_range_list + open_value_range
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open_value_range { $$ = $1; }
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| open_range_list ',' open_value_range { $$ = $1;$1->addNext($3); }
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;
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open_value_range<nodep>: // ==IEEE: open_value_range
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value_range { $$ = $1; }
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;
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value_range<nodep>: // ==IEEE: value_range
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expr { $$ = $1; }
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| '[' expr ':' expr ']' { $$ = new AstInsideRange($3,$2,$4); }
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;
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caseCondList<nodep>: // IEEE: part of case_item
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expr { $$ = $1; }
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| caseCondList ',' expr { $$ = $1;$1->addNext($3); }
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@ -2757,7 +2772,7 @@ expr<nodep>: // IEEE: part of expression/constant_expression/primary
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| ~l~expr '?' ~r~expr ':' ~r~expr { $$ = new AstCond($2,$1,$3,$5); }
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//
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// // IEEE: inside_expression
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//UNSUP ~l~expr yINSIDE '{' open_range_list '}' { UNSUP }
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| ~l~expr yINSIDE '{' open_range_list '}' { $$ = new AstInside($2,$1,$4); }
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//
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// // IEEE: tagged_union_expression
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//UNSUP yTAGGED id/*member*/ %prec prTAGGED { UNSUP }
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18
test_regress/t/t_inside.pl
Executable file
18
test_regress/t/t_inside.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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69
test_regress/t/t_inside.v
Normal file
69
test_regress/t/t_inside.v
Normal file
@ -0,0 +1,69 @@
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// DESCRIPTION::Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Wilson Snyder.
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module t;
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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typedef enum logic [1:0]
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{ ZERO = 2'd0,
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ONE = 2'd1,
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TWO = 2'd2,
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THREE = 2'd3,
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XXX = 2'dx
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} num_t;
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function automatic logic is_odd;
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input en;
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input num_t number;
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case (en)
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1'b1: begin
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unique if (number inside {ONE, THREE})
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is_odd = 1'b1;
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else if (number inside {ZERO, TWO})
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is_odd = 1'b0;
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else
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is_odd = 1'bx;
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end
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1'b0: is_odd = 1'bx;
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default: is_odd = 1'bx;
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endcase
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endfunction
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initial begin
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`checkh ((4'd4 inside {4'd1,4'd5}), 1'b0);
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`checkh ((4'd4 inside {4'd1,4'd4}), 1'b1);
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//
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`checkh ((4'b1011 inside {4'b1001}), 1'b0);
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`checkh ((4'b1011 inside {4'b1xx1}), 1'b1); // Uses ==?
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`checkh ((4'b1001 inside {4'b1xx1}), 1'b1); // Uses ==?
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`checkh ((4'b1001 inside {4'b1??1}), 1'b1);
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`ifndef VERILATOR
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`checkh ((4'b1z11 inside {4'b11?1, 4'b1011}),1'bx);
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`endif
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// Range
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`checkh ((4'd4 inside {[4'd5:4'd3], [4'd10:4'd8]}), 1'b0); // If left of colon < never matches
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`checkh ((4'd3 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
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`checkh ((4'd4 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
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`checkh ((4'd5 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
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//
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// Unsupported $ bound
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//
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// Unsupported if unpacked array, elements tranversed
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//int unpackedarray [$] = '{8,9};
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//( expr inside {2, 3, unpackedarray}) // { 2,3,8,9}
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//
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`checkh (is_odd(1'b1, ZERO), 1'd0);
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`checkh (is_odd(1'b1, ONE), 1'd1);
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`checkh (is_odd(1'b1, TWO), 1'd0);
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`checkh (is_odd(1'b1, THREE),1'd1);
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`ifndef VERILATOR
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`checkh (is_odd(1'b1, XXX), 1'dx);
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`endif
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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