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78 lines
1.2 KiB
Verilog
78 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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v95 v95 ();
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v01 v01 ();
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v05 v05 ();
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s05 s05 ();
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s09 s09 ();
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s12 s12 ();
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s17 s17 ();
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a23 a23 ();
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initial begin
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$finish;
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end
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endmodule
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`begin_keywords "1364-1995"
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module v95;
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integer signed; initial signed = 1;
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endmodule
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`end_keywords
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`begin_keywords "1364-2001"
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module v01;
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integer bit; initial bit = 1;
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endmodule
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`end_keywords
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`begin_keywords "1364-2005"
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module v05;
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integer final; initial final = 1;
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endmodule
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`end_keywords
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`begin_keywords "1800-2005"
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module s05;
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integer global; initial global = 1;
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endmodule
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`end_keywords
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`begin_keywords "1800-2009"
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module s09;
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integer soft; initial soft = 1;
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endmodule
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`end_keywords
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`begin_keywords "1800-2012"
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module s12;
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final begin
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$write("*-* All Finished *-*\n");
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end
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endmodule
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`end_keywords
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`begin_keywords "1800-2017"
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module s17;
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final begin
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$write("*-* All Finished *-*\n");
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end
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endmodule
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`end_keywords
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`begin_keywords "VAMS-2.3"
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module a23;
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real foo; initial foo = sqrt(2.0);
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endmodule
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`end_keywords
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