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Support IEEE 1800-2017 as default language.
This commit is contained in:
Wilson Snyder
parent
fc48008c1c
commit
2d580e6939
2
Changes
2
Changes
@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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* Verilator 3.921 devel
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** Support IEEE 1800-2017 as default language.
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*** Support trig functions ($sin() etc), bug1281. [Patrick Stewart]
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*** Support calling system functions as tasks, bug1285. [Joel Holdsworth]
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@ -259,6 +259,7 @@ descriptions in the next sections for more information.
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+1800-2005ext+<ext> Use SystemVerilog 2005 with file extension <ext>
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+1800-2009ext+<ext> Use SystemVerilog 2009 with file extension <ext>
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+1800-2012ext+<ext> Use SystemVerilog 2012 with file extension <ext>
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+1800-2017ext+<ext> Use SystemVerilog 2017 with file extension <ext>
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--assert Enable all assertions
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--autoflush Flush streams after all $displays
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--bbox-sys Blackbox unknown $system calls
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@ -345,7 +346,7 @@ descriptions in the next sections for more information.
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--stats Create statistics file
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--stats-vars Provide statistics on variables
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-sv Enable SystemVerilog parsing
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+systemverilogext+<ext> Synonym for +1800-2012ext+<ext>
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+systemverilogext+<ext> Synonym for +1800-2017ext+<ext>
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--top-module <topname> Name of top level input module
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--trace Enable waveform creation
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--trace-depth <levels> Depth of tracing
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@ -412,6 +413,8 @@ with the --exe option.
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=item +1800-2012ext+I<ext>
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=item +1800-2017ext+I<ext>
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Specifies the language standard to be used with a specific filename
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extension, I<ext>.
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@ -661,7 +664,7 @@ produce more detailed messages.
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Select the language to be used by default when first processing each
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Verilog file. The language value must be "1364-1995", "1364-2001",
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"1364-2005", "1800-2005", "1800-2009" or "1800-2012".
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"1364-2005", "1800-2005", "1800-2009", "1800-2012" or "1800-2017".
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Any language associated with a particular file extension (see the various
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+I<lang>ext+ options) will be used in preference to the language specified
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@ -674,7 +677,7 @@ legacy mixed language designs, the various +I<lang>ext+ options should be
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used.
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If no language is specified, either by this flag or +I<lang>ext+ options,
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then the latest SystemVerilog language (IEEE 1800-2012) is used.
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then the latest SystemVerilog language (IEEE 1800-2017) is used.
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=item +define+I<var>=I<value>
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@ -1152,7 +1155,7 @@ compatibility with other simulators.
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=item +systemverilogext+I<ext>
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A synonym for C<+1800-2012ext+>I<ext>.
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A synonym for C<+1800-2017ext+>I<ext>.
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=item --top-module I<topname>
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@ -2216,6 +2219,11 @@ Verilator currently has some support for SystemVerilog synthesis
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constructs. As SystemVerilog features enter common usage they are added;
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please file a bug if a feature you need is missing.
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=head2 SystemVerilog 2017 (IEEE 1800-2017) Support
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Verilator supports the 2017 "for" loop constructs, and several minor
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cleanups made in 1800-2017.
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=head2 Verilog AMS Support
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Verilator implements a very small subset of Verilog AMS (Verilog Analog and
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@ -7,7 +7,7 @@
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* This file contains the constant definitions, structure definitions,
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* and routine declarations used by SystemVerilog DPI.
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*
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* This file is from the SystemVerilog IEEE 1800-2012 Annex I.
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* This file is from the SystemVerilog IEEE 1800-2017 Annex I.
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*/
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#ifndef INCLUDED_SVDPI
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@ -117,7 +117,7 @@ typedef uint32_t svBitVecVal;
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/*
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* Return implementation version information string ("1800-2005" or "SV3.1a").
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*/
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XXTERN const char* svDpiVersion();
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XXTERN const char* svDpiVersion( void );
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/* a handle to a scope (an instance of a module or interface) */
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XXTERN typedef void* svScope;
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@ -241,28 +241,28 @@ XXTERN void svGetLogicArrElem2VecVal(svLogicVecVal* d, const svOpenArrayHandle s
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XXTERN void svGetLogicArrElem3VecVal(svLogicVecVal* d, const svOpenArrayHandle s,
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int indx1, int indx2, int indx3);
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XXTERN svBit svGetBitArrElem(const svOpenArrayHandle s, int indx1, ...);
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XXTERN svBit svGetBitArrElem1(const svOpenArrayHandle s, int indx1);
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XXTERN svBit svGetBitArrElem2(const svOpenArrayHandle s, int indx1, int indx2);
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XXTERN svBit svGetBitArrElem3(const svOpenArrayHandle s, int indx1, int indx2,
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XXTERN svBit svGetBitArrElem(const svOpenArrayHandle s, int indx1, ...);
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XXTERN svBit svGetBitArrElem1(const svOpenArrayHandle s, int indx1);
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XXTERN svBit svGetBitArrElem2(const svOpenArrayHandle s, int indx1, int indx2);
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XXTERN svBit svGetBitArrElem3(const svOpenArrayHandle s, int indx1, int indx2,
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int indx3);
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XXTERN svLogic svGetLogicArrElem(const svOpenArrayHandle s, int indx1, ...);
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XXTERN svLogic svGetLogicArrElem1(const svOpenArrayHandle s, int indx1);
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XXTERN svLogic svGetLogicArrElem2(const svOpenArrayHandle s, int indx1, int indx2);
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XXTERN svLogic svGetLogicArrElem3(const svOpenArrayHandle s, int indx1, int indx2,
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XXTERN svLogic svGetLogicArrElem(const svOpenArrayHandle s, int indx1, ...);
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XXTERN svLogic svGetLogicArrElem1(const svOpenArrayHandle s, int indx1);
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XXTERN svLogic svGetLogicArrElem2(const svOpenArrayHandle s, int indx1, int indx2);
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XXTERN svLogic svGetLogicArrElem3(const svOpenArrayHandle s, int indx1, int indx2,
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int indx3);
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XXTERN void svPutLogicArrElem(const svOpenArrayHandle d, svLogic value, int indx1,
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XXTERN void svPutLogicArrElem(const svOpenArrayHandle d, svLogic value, int indx1,
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...);
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XXTERN void svPutLogicArrElem1(const svOpenArrayHandle d, svLogic value, int indx1);
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XXTERN void svPutLogicArrElem2(const svOpenArrayHandle d, svLogic value, int indx1,
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XXTERN void svPutLogicArrElem1(const svOpenArrayHandle d, svLogic value, int indx1);
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XXTERN void svPutLogicArrElem2(const svOpenArrayHandle d, svLogic value, int indx1,
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int indx2);
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XXTERN void svPutLogicArrElem3(const svOpenArrayHandle d, svLogic value, int indx1,
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XXTERN void svPutLogicArrElem3(const svOpenArrayHandle d, svLogic value, int indx1,
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int indx2, int indx3);
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XXTERN void svPutBitArrElem(const svOpenArrayHandle d, svBit value, int indx1, ...);
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XXTERN void svPutBitArrElem1(const svOpenArrayHandle d, svBit value, int indx1);
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XXTERN void svPutBitArrElem2(const svOpenArrayHandle d, svBit value, int indx1,
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XXTERN void svPutBitArrElem(const svOpenArrayHandle d, svBit value, int indx1, ...);
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XXTERN void svPutBitArrElem1(const svOpenArrayHandle d, svBit value, int indx1);
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XXTERN void svPutBitArrElem2(const svOpenArrayHandle d, svBit value, int indx1,
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int indx2);
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XXTERN void svPutBitArrElem3(const svOpenArrayHandle d, svBit value, int indx1,
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XXTERN void svPutBitArrElem3(const svOpenArrayHandle d, svBit value, int indx1,
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int indx2, int indx3);
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/* Functions for working with DPI context */
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@ -273,7 +273,7 @@ XXTERN void svPutBitArrElem3(const svOpenArrayHandle d, svBit value, int indx1
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* is the scope of the function's declaration site, not call site.
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* Returns NULL if called from C code that is *not* an imported function.
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*/
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XXTERN svScope svGetScope();
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XXTERN svScope svGetScope( void );
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/*
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* Set context for subsequent export function execution.
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@ -337,7 +337,7 @@ XXTERN int svGetCallerInfo(const char** fileName, int *lineNumber);
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* Returns 1 if the current execution thread is in the disabled state.
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* Disable protocol must be adhered to if in the disabled state.
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*/
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XXTERN int svIsDisabledState();
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XXTERN int svIsDisabledState( void );
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/*
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* Imported functions call this API function during disable processing to
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@ -345,7 +345,7 @@ XXTERN int svIsDisabledState();
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* This function must be called before returning from an imported function that is
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* in the disabled state.
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*/
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XXTERN void svAckDisabledState();
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XXTERN void svAckDisabledState( void );
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/*
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**********************************************************
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@ -1,7 +1,7 @@
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/*******************************************************************************
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* vpi_user.h
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*
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* IEEE Std 1800-2012 Programming Language Interface (PLI)
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* IEEE Std 1800-2017 Programming Language Interface (PLI)
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*
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* This file contains the constant definitions, structure definitions, and
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* routine declarations used by the SystemVerilog Verification Procedural
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@ -251,7 +251,7 @@ typedef PLI_UINT32 *vpiHandle;
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#define vpiModPathOut 96 /* output terminal of a module path */
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#define vpiOperand 97 /* operand of expression */
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#define vpiPortInst 98 /* connected port instance */
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#define vpiProcess 99 /* process in module */
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#define vpiProcess 99 /* process in module, program or interface */
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#define vpiVariables 100 /* variables in module */
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#define vpiUse 101 /* usage */
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@ -978,7 +978,7 @@ XXTERN vpiHandle vpi_handle_by_multi_index PROTO_PARAMS((vpiHandle obj,
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/****************************** GLOBAL VARIABLES ******************************/
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PLI_VEXTERN PLI_DLLESPEC void (*vlog_startup_routines[])();
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PLI_VEXTERN PLI_DLLESPEC void (*vlog_startup_routines[])( void );
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/* array of function pointers, last pointer should be null */
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@ -42,6 +42,7 @@ public:
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L1800_2005,
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L1800_2009,
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L1800_2012,
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L1800_2017,
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// ***Add new elements below also***
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_ENUM_END
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};
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@ -54,12 +55,14 @@ public:
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"1364-2005",
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"1800-2005",
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"1800-2009",
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"1800-2012"
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"1800-2012",
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"1800-2017"
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};
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return names[m_e];
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};
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static V3LangCode mostRecent() { return V3LangCode(L1800_2012); }
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bool systemVerilog() const { return m_e == L1800_2005 || m_e == L1800_2009 || m_e == L1800_2012; }
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static V3LangCode mostRecent() { return V3LangCode(L1800_2017); }
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bool systemVerilog() const { return m_e == L1800_2005 || m_e == L1800_2009
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|| m_e == L1800_2012 || m_e == L1800_2017; }
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bool legal() const { return m_e != L_ERROR; }
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//
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enum en m_e;
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@ -142,7 +142,7 @@ V3Number::V3Number (FileLine* fileline, const char* sourcep) {
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if (!m_sized) {
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static int warned = false;
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if (!warned++) {
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m_fileline->v3error("As that number was unsized ('d...) it is limited to 32 bits (IEEE 2012 5.7.1)");
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m_fileline->v3error("As that number was unsized ('d...) it is limited to 32 bits (IEEE 2017 5.7.1)");
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}
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}
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while (*(cp+1)) cp++; // Skip ahead so don't get multiple warnings
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@ -604,7 +604,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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else if ( !strncmp (sw, "+incdir+", 8)) {
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addIncDirUser (parseFileArg(optdir, string (sw+strlen("+incdir+"))));
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}
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else if (parseLangExt(sw, "+systemverilogext+", V3LangCode::L1800_2012)
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else if (parseLangExt(sw, "+systemverilogext+", V3LangCode::L1800_2017)
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|| parseLangExt(sw, "+verilog1995ext+", V3LangCode::L1364_1995)
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|| parseLangExt(sw, "+verilog2001ext+", V3LangCode::L1364_2001)
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|| parseLangExt(sw, "+1364-1995ext+", V3LangCode::L1364_1995)
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@ -612,7 +612,8 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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|| parseLangExt(sw, "+1364-2005ext+", V3LangCode::L1364_2005)
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|| parseLangExt(sw, "+1800-2005ext+", V3LangCode::L1800_2005)
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|| parseLangExt(sw, "+1800-2009ext+", V3LangCode::L1800_2009)
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|| parseLangExt(sw, "+1800-2012ext+", V3LangCode::L1800_2012)) {
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|| parseLangExt(sw, "+1800-2012ext+", V3LangCode::L1800_2012)
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|| parseLangExt(sw, "+1800-2017ext+", V3LangCode::L1800_2017)) {
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// Nothing to do here - all done in the test
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}
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@ -928,7 +928,7 @@ private:
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&& portp->dtypep()->basicp()
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&& portp->dtypep()->basicp()->keyword().isDpiUnreturnable()) {
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portp->v3error("DPI function may not return type "<<portp->basicp()->prettyTypeName()
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<<" (IEEE 2012 35.5.5)");
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<<" (IEEE 2017 35.5.5)");
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}
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portp->unlinkFrBack();
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rtnvarp = portp;
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@ -446,7 +446,7 @@ private:
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if (!constp) { nodep->v3error("Replication value isn't a constant."); return; }
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uint32_t times = constp->toUInt();
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if (times==0 && !nodep->backp()->castConcat()) { // Concat Visitor will clean it up.
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nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 2012 11.4.12.1)"); times=1;
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nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 2017 11.4.12.1)"); times=1;
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}
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if (nodep->lhsp()->isString()) {
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AstNode* newp = new AstReplicateN(nodep->fileline(),nodep->lhsp()->unlinkFrBack(),
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@ -477,7 +477,7 @@ private:
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if (!constp) { nodep->v3error("Replication value isn't a constant."); return; }
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uint32_t times = constp->toUInt();
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if (times==0 && !nodep->backp()->castConcat()) { // Concat Visitor will clean it up.
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nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 2012 11.4.12.1)");
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nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE 2017 11.4.12.1)");
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}
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nodep->dtypeSetString();
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}
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@ -1298,7 +1298,7 @@ private:
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}
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if (!itemp->valuep()) {
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if (num.isEqZero() && itemp != nodep->itemsp())
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itemp->v3error("Enum value illegally wrapped around (IEEE 2012 6.19)");
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itemp->v3error("Enum value illegally wrapped around (IEEE 2017 6.19)");
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if (!nodep->dtypep()->basicp()
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&& !nodep->dtypep()->basicp()->keyword().isIntNumeric()) {
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itemp->v3error("Enum names without values only allowed on numeric types");
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@ -32,7 +32,7 @@
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extern void yyerror(const char*);
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extern void yyerrorf(const char* format, ...);
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#define STATE_VERILOG_RECENT S12 // State name for most recent Verilog Version
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#define STATE_VERILOG_RECENT S17 // State name for most recent Verilog Version
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#define PARSEP V3ParseImp::parsep()
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#define SYMP PARSEP->symp()
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@ -126,7 +126,7 @@ void yyerror(const char* errmsg) {
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static int warned = false;
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if (!warned++) {
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PARSEP->fileline()->v3error("Perhaps '"+*PARSEP->prevBisonVal().strp
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+"' is a package which needs to be predeclared? (IEEE 2012 26.3)");
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+"' is a package which needs to be predeclared? (IEEE 2017 26.3)");
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}
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}
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}
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@ -154,7 +154,7 @@ void yyerrorf(const char* format, ...) {
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%a 15000
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%o 25000
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%s V95 V01 V05 S05 S09 S12
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%s V95 V01 V05 S05 S09 S12 S17
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%s STRING ATTRMODE TABLE
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%s VA5 SAX VLT
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%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
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@ -200,7 +200,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* Verilog 1995 */
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<V95,V01,V05,VA5,S05,S09,S12,SAX>{
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
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{ws} { } /* otherwise ignore white-space */
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{crnl} { NEXTLINE(); } /* Count line numbers */
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/* Extensions to Verilog set, some specified by PSL */
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@ -390,7 +390,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* Verilog 2001 */
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<V01,V05,VA5,S05,S09,S12,SAX>{
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<V01,V05,VA5,S05,S09,S12,S17,SAX>{
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/* System Tasks */
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"$signed" { FL; return yD_SIGNED; }
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"$unsigned" { FL; return yD_UNSIGNED; }
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@ -421,13 +421,13 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* Verilog 2005 */
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<V05,S05,S09,S12,SAX>{
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<V05,S05,S09,S12,S17,SAX>{
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/* Keywords */
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"uwire" { FL; return yWIRE; }
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}
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/* System Verilog 2005 */
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<S05,S09,S12,SAX>{
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<S05,S09,S12,S17,SAX>{
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/* System Tasks */
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"$bits" { FL; return yD_BITS; }
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"$clog2" { FL; return yD_CLOG2; }
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@ -552,7 +552,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* SystemVerilog 2009 */
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<S09,S12,SAX>{
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<S09,S12,S17,SAX>{
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/* Keywords */
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"global" { FL; return yGLOBAL__LEX; }
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"unique0" { FL; return yUNIQUE0; }
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@ -581,7 +581,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* System Verilog 2012 */
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<S12,SAX>{
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<S12,S17,SAX>{
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/* Keywords */
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"implements" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
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"interconnect" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
|
||||
@ -589,8 +589,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
"soft" { yyerrorf("Unsupported: SystemVerilog 2012 reserved word not implemented: %s",yytext); }
|
||||
}
|
||||
|
||||
/* System Verilog 2017 */
|
||||
/* No new keywords */
|
||||
|
||||
/* Default PLI rule */
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SAX>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
||||
"$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext,yyleng);
|
||||
yylval.strp = PARSEP->newString(AstNode::encodeName(str));
|
||||
// Lookup unencoded name including the $, to avoid hitting normal signals
|
||||
@ -697,7 +700,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
/* Meta comments */
|
||||
|
||||
/* Converted from //{cmt}verilator ...{cmt} by preprocessor */
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SAX>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
||||
"/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */
|
||||
"/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; }
|
||||
"/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; }
|
||||
@ -735,7 +738,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
/************************************************************************/
|
||||
|
||||
/* Single character operator thingies */
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SAX>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
||||
"{" { FL; return yytext[0]; }
|
||||
"}" { FL; return yytext[0]; }
|
||||
"!" { FL; return yytext[0]; }
|
||||
@ -769,7 +772,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
/* Operators and multi-character symbols */
|
||||
|
||||
/* Verilog 1995 Operators */
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SAX>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
||||
"&&" { FL; return yP_ANDAND; }
|
||||
"||" { FL; return yP_OROR; }
|
||||
"<=" { FL; return yP_LTE; }
|
||||
@ -791,7 +794,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
}
|
||||
|
||||
/* Verilog 2001 Operators */
|
||||
<V01,V05,VA5,S05,S09,S12,SAX>{
|
||||
<V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
||||
"<<<" { FL; return yP_SLEFT; }
|
||||
">>>" { FL; return yP_SSRIGHT; }
|
||||
"**" { FL; return yP_POW; }
|
||||
@ -804,7 +807,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
}
|
||||
|
||||
/* SystemVerilog Operators */
|
||||
<S05,S09,S12,SAX>{
|
||||
<S05,S09,S12,S17,SAX>{
|
||||
"'" { FL; return yP_TICK; }
|
||||
"'{" { FL; return yP_TICKBRA; }
|
||||
"==?" { FL; return yP_WILDEQUAL; }
|
||||
@ -838,7 +841,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
}
|
||||
|
||||
/* Identifiers and numbers */
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SAX,VLT>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
|
||||
{escid} { FL; yylval.strp = PARSEP->newString
|
||||
(AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash
|
||||
return yaID__LEX;
|
||||
@ -911,7 +914,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
/************************************************************************/
|
||||
/* Attributes */
|
||||
/* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SAX>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
|
||||
"(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */
|
||||
}
|
||||
|
||||
@ -928,7 +931,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
/* Preprocessor */
|
||||
/* Common for all SYSC header states */
|
||||
/* OPTIMIZE: we return one per line, make it one for the entire block */
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
|
||||
"`accelerate" { } // Verilog-XL compatibility
|
||||
"`autoexpand_vectornets" { } // Verilog-XL compatibility
|
||||
"`celldefine" { PARSEP->inCellDefine(true); }
|
||||
@ -972,6 +975,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
"`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); }
|
||||
"`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); }
|
||||
"`begin_keywords"[ \t]*\"1800-2012\" { yy_push_state(S12); PARSEP->pushBeginKeywords(YY_START); }
|
||||
"`begin_keywords"[ \t]*\"1800-2017\" { yy_push_state(S17); PARSEP->pushBeginKeywords(YY_START); }
|
||||
"`begin_keywords"[ \t]*\"1800[+]VAMS\" { yy_push_state(SAX); PARSEP->pushBeginKeywords(YY_START); } /*Latest SV*/
|
||||
"`end_keywords" { yy_pop_state(); if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
|
||||
|
||||
@ -1003,7 +1007,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
|
||||
/************************************************************************/
|
||||
/* Default rules - leave last */
|
||||
|
||||
<V95,V01,V05,VA5,S05,S09,S12,SAX,VLT>{
|
||||
<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
|
||||
"`"[a-zA-Z_0-9]+ { FL; yyerrorf("Define or directive not defined: %s",yytext); }
|
||||
"//"[^\n]* { } /* throw away single line comments */
|
||||
. { FL; return yytext[0]; } /* return single char ops. */
|
||||
|
||||
@ -743,7 +743,6 @@ package_or_generate_item_declaration<nodep>: // ==IEEE: package_or_generate_item
|
||||
| local_parameter_declaration ';' { $$ = $1; }
|
||||
| parameter_declaration ';' { $$ = $1; }
|
||||
//UNSUP covergroup_declaration { $$ = $1; }
|
||||
//UNSUP overload_declaration { $$ = $1; }
|
||||
//UNSUP assertion_item_declaration { $$ = $1; }
|
||||
| ';' { $$ = NULL; }
|
||||
;
|
||||
@ -2275,7 +2274,6 @@ block_item_declaration<nodep>: // ==IEEE: block_item_declaration
|
||||
data_declaration { $$ = $1; }
|
||||
| local_parameter_declaration ';' { $$ = $1; }
|
||||
| parameter_declaration ';' { $$ = $1; }
|
||||
//UNSUP overload_declaration { $$ = $1; }
|
||||
//UNSUP let_declaration { $$ = $1; }
|
||||
;
|
||||
|
||||
@ -2374,8 +2372,7 @@ statement_item<nodep>: // IEEE: statement_item
|
||||
| yREPEAT '(' expr ')' stmtBlock { $$ = new AstRepeat($1,$3,$5);}
|
||||
| yWHILE '(' expr ')' stmtBlock { $$ = new AstWhile($1,$3,$5);}
|
||||
// // for's first ';' is in for_initalization
|
||||
| yFOR '(' for_initialization expr ';' for_stepE ')' stmtBlock
|
||||
{ $$ = new AstBegin($1,"",$3); $3->addNext(new AstWhile($1, $4,$8,$6)); }
|
||||
| statementFor { $$ = $1; }
|
||||
| yDO stmtBlock yWHILE '(' expr ')' ';' { $$ = $2->cloneTree(true); $$->addNext(new AstWhile($1,$5,$2));}
|
||||
// // IEEE says array_identifier here, but dotted accepted in VMM and 1800-2009
|
||||
| yFOREACH '(' idClassForeach '[' loop_variables ']' ')' stmtBlock { $$ = new AstForeach($1,$3,$5,$8); }
|
||||
@ -2423,6 +2420,15 @@ statement_item<nodep>: // IEEE: statement_item
|
||||
| error ';' { $$ = NULL; }
|
||||
;
|
||||
|
||||
statementFor<beginp>: // IEEE: part of statement
|
||||
yFOR '(' for_initialization expr ';' for_stepE ')' stmtBlock
|
||||
{ $$ = new AstBegin($1,"",$3);
|
||||
$$->addStmtsp(new AstWhile($1, $4,$8,$6)); }
|
||||
| yFOR '(' for_initialization ';' for_stepE ')' stmtBlock
|
||||
{ $$ = new AstBegin($1,"",$3);
|
||||
$$->addStmtsp(new AstWhile($1, new AstConst($1,AstConst::LogicTrue()),$7,$5)); }
|
||||
;
|
||||
|
||||
statementVerilatorPragmas<nodep>:
|
||||
yVL_COVERAGE_BLOCK_OFF { $$ = new AstPragma($1,AstPragmaType::COVERAGE_BLOCK_OFF); }
|
||||
;
|
||||
@ -2597,6 +2603,7 @@ for_initialization<nodep>: // ==IEEE: for_initialization + for_variable_declarat
|
||||
$$ = VARDONEA($<fl>2,*$2,NULL,NULL);
|
||||
$$->addNext(new AstAssign($3,new AstVarRef($3,*$2,true),$4));}
|
||||
| varRefBase '=' expr ';' { $$ = new AstAssign($2,$1,$3); }
|
||||
| ';' { $$ = NULL; }
|
||||
//UNSUP: List of initializations
|
||||
;
|
||||
|
||||
@ -3120,7 +3127,7 @@ expr<nodep>: // IEEE: part of expression/constant_expression/primary
|
||||
//
|
||||
// // IEEE: "... hierarchical_identifier select" see below
|
||||
//
|
||||
// // IEEE: empty_queue
|
||||
// // IEEE: empty_queue (IEEE 1800-2017 empty_unpacked_array_concatenation)
|
||||
//UNSUP '{' '}'
|
||||
//
|
||||
// // IEEE: concatenation/constant_concatenation
|
||||
|
||||
@ -11,7 +11,7 @@ compile (
|
||||
v_flags2 => ["--lint-only"],
|
||||
fails=>$Self->{v3},
|
||||
expect=>
|
||||
'%Error: t/t_dpi_logic_bad.v:\d+: DPI function may not return type BASICDTYPE \'logic\' \(IEEE 2012 35.5.5\)
|
||||
'%Error: t/t_dpi_logic_bad.v:\d+: DPI function may not return type BASICDTYPE \'logic\' \(IEEE 2017 35.5.5\)
|
||||
%Error: Exiting due to .*'
|
||||
);
|
||||
|
||||
|
||||
@ -78,6 +78,22 @@ module t (/*AUTOARG*/
|
||||
if (i !== -1) $stop;
|
||||
if (loops !== 17) $stop;
|
||||
//
|
||||
// 1800-2017 optionals init/expr/incr
|
||||
loops = 0;
|
||||
i = 0;
|
||||
for (; i<10; ++i) ++loops;
|
||||
if (loops !== 10) $stop;
|
||||
//
|
||||
loops = 0;
|
||||
i = 0;
|
||||
for (i=0; i<10; ) begin ++loops; ++i; end
|
||||
if (loops !== 10) $stop;
|
||||
//
|
||||
loops = 0;
|
||||
i = 0;
|
||||
for (; ; ++i) begin ++loops; break; end
|
||||
if (loops !== 1) $stop;
|
||||
//
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
@ -17,7 +17,7 @@ compile (
|
||||
make_main => 0,
|
||||
expect=> quotemeta(
|
||||
qq{%Error: t/t_lint_pkg_colon_bad.v:6: syntax error, unexpected ::, expecting ')' or ','
|
||||
%Error: t/t_lint_pkg_colon_bad.v:6: Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 2012 26.3)
|
||||
%Error: t/t_lint_pkg_colon_bad.v:6: Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 2017 26.3)
|
||||
%Error: t/t_lint_pkg_colon_bad.v:7: syntax error, unexpected ::, expecting ',' or ';'
|
||||
}).'%Error: Exiting due to.*'
|
||||
);
|
||||
|
||||
@ -17,7 +17,7 @@ compile (
|
||||
make_main => 0,
|
||||
expect=> quotemeta(
|
||||
qq{%Error: t/t_lint_unsized_bad.v:7: Too many digits for 32 bit number: 'd123456789123456789123456789
|
||||
%Error: t/t_lint_unsized_bad.v:7: As that number was unsized ('d...) it is limited to 32 bits (IEEE 2012 5.7.1)
|
||||
%Error: t/t_lint_unsized_bad.v:7: As that number was unsized ('d...) it is limited to 32 bits (IEEE 2017 5.7.1)
|
||||
}).'%Error: Exiting due to.*'
|
||||
);
|
||||
|
||||
|
||||
@ -129,7 +129,7 @@ module t (/*AUTOARG*/
|
||||
if (bug764_p11 !== 4'b000x) $stop;
|
||||
if (~& bug764_p11 !== 1'b1) $stop;
|
||||
//verilator lint_on WIDTH
|
||||
// However IEEE says for constants in 2012 5.7.1 that smaller-sizes do extend
|
||||
// However IEEE 2017 5.7.1 says for constants that smaller-sizes do extend
|
||||
if (4'bx !== 4'bxxxx) $stop;
|
||||
if (4'bz !== 4'bzzzz) $stop;
|
||||
if (4'b1 !== 4'b0001) $stop;
|
||||
|
||||
@ -14,8 +14,10 @@ module t (/*AUTOARG*/
|
||||
v05 v05 ();
|
||||
s05 s05 ();
|
||||
s09 s09 ();
|
||||
a23 a23 ();
|
||||
s12 s12 ();
|
||||
s17 s17 ();
|
||||
|
||||
a23 a23 ();
|
||||
|
||||
initial begin
|
||||
$finish;
|
||||
@ -60,6 +62,14 @@ module s12;
|
||||
endmodule
|
||||
`end_keywords
|
||||
|
||||
`begin_keywords "1800-2017"
|
||||
module s17;
|
||||
final begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
end
|
||||
endmodule
|
||||
`end_keywords
|
||||
|
||||
`begin_keywords "VAMS-2.3"
|
||||
module a23;
|
||||
real foo; initial foo = sqrt(2.0);
|
||||
|
||||
@ -2,11 +2,11 @@
|
||||
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
|
||||
<verilator_xml>
|
||||
<files>
|
||||
<file id="a" filename="AstRoot" language="1800-2012"/>
|
||||
<file id="b" filename="COMMAND_LINE" language="1800-2012"/>
|
||||
<file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2012"/>
|
||||
<file id="d" filename="input.vc" language="1800-2012"/>
|
||||
<file id="e" filename="t/t_xml_first.v" language="1800-2012"/>
|
||||
<file id="a" filename="AstRoot" language="1800-2017"/>
|
||||
<file id="b" filename="COMMAND_LINE" language="1800-2017"/>
|
||||
<file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2017"/>
|
||||
<file id="d" filename="input.vc" language="1800-2017"/>
|
||||
<file id="e" filename="t/t_xml_first.v" language="1800-2017"/>
|
||||
</files>
|
||||
<netlist>
|
||||
<module fl="e6" name="t" topModule="1">
|
||||
|
||||
@ -2,11 +2,11 @@
|
||||
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
|
||||
<verilator_xml>
|
||||
<files>
|
||||
<file id="a" filename="AstRoot" language="1800-2012"/>
|
||||
<file id="b" filename="COMMAND_LINE" language="1800-2012"/>
|
||||
<file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2012"/>
|
||||
<file id="d" filename="input.vc" language="1800-2012"/>
|
||||
<file id="e" filename="t/t_xml_tag.v" language="1800-2012"/>
|
||||
<file id="a" filename="AstRoot" language="1800-2017"/>
|
||||
<file id="b" filename="COMMAND_LINE" language="1800-2017"/>
|
||||
<file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2017"/>
|
||||
<file id="d" filename="input.vc" language="1800-2017"/>
|
||||
<file id="e" filename="t/t_xml_tag.v" language="1800-2017"/>
|
||||
</files>
|
||||
<netlist>
|
||||
<module fl="e6" name="m">
|
||||
|
||||
Loading…
Reference in New Issue
Block a user