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32 lines
601 B
Verilog
32 lines
601 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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value
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);
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input [1:0] value;
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sub #(.CASEVAL(2'h0)) p0 (.value);
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sub #(.CASEVAL(2'h1)) p1 (.value);
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sub #(.CASEVAL(2'h2)) p2 (.value);
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sub #(.CASEVAL(2'h3)) p3 (.value);
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endmodule
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module sub
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(
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input [1:0] value);
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parameter [1:0] CASEVAL = 2'h0;
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always_comb begin
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case (value)
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CASEVAL: ;
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2'h2: $stop;
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default: ;
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endcase
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end
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endmodule
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