Tests: New scope-relevant tests, towards bug1305.

test_regress/t/t_clk_scope_bad.out

@@ -0,0 +1,3 @@
+%Warning-CLKDATA: t/t_clk_scope_bad.v:35: Clock used as data (on rhs of assignment) in sequential block clk
+%Warning-CLKDATA: Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message.
+%Error: Exiting due to

test_regress/t/t_clk_scope_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    v_flags2 => ["--lint-only"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_clk_scope_bad.v

@@ -0,0 +1,37 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in
+   );
+
+   input clk;
+   input [2:0] in;
+   output [2:0] out;
+
+   logic [2:0] r_in;
+   always_ff @ (posedge clk) r_in <= in;
+
+   flop p0 (.clk(clk), .d(r_in[0]), .q(out[0]));
+   flop p2 (.clk(r_in[1]), .d(clk), .q(out[1]));
+   flop p1 (.clk(clk), .d(r_in[2]), .q(out[2]));
+
+endmodule
+
+module flop
+  (
+   input  d,
+   input  clk,
+   output logic q);
+
+   // verilator no_inline_module
+
+   always_ff @ (posedge clk) begin
+      q <= d;
+   end
+endmodule

test_regress/t/t_param_scope_bad.out

@@ -0,0 +1,3 @@
+%Warning-CASEOVERLAP: t/t_param_scope_bad.v:27: Case values overlap (example pattern 0x2)
+%Warning-CASEOVERLAP: Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message.
+%Error: Exiting due to

test_regress/t/t_param_scope_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    v_flags2 => ["--lint-only"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_param_scope_bad.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   value
+   );
+   input [1:0] value;
+
+   sub #(.CASEVAL(2'h0)) p0 (.value);
+   sub #(.CASEVAL(2'h1)) p1 (.value);
+   sub #(.CASEVAL(2'h2)) p2 (.value);
+   sub #(.CASEVAL(2'h3)) p3 (.value);
+
+endmodule
+
+module sub
+  (
+   input [1:0] value);
+
+   parameter [1:0] CASEVAL = 2'h0;
+   always_comb begin
+      case (value)
+        CASEVAL: ;
+        2'h2: $stop;
+        default: ;
+      endcase
+   end
+endmodule