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36 lines
2.0 KiB
Plaintext
36 lines
2.0 KiB
Plaintext
%Warning-STMTDLY: t/t_net_delay.v:14:11: Ignoring delay on this statement due to --no-timing
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: ... note: In instance 't'
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14 | always #2 clk = ~clk;
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| ^
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... For warning description see https://verilator.org/warn/STMTDLY?v=latest
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... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
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%Warning-STMTDLY: t/t_net_delay.v:20:14: Ignoring delay on this statement due to --no-timing
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: ... note: In instance 't'
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20 | wire[3:0] #3 val1;
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| ^
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%Warning-STMTDLY: t/t_net_delay.v:21:14: Ignoring delay on this statement due to --no-timing
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: ... note: In instance 't'
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21 | wire[3:0] #3 val2;
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| ^
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%Warning-ASSIGNDLY: t/t_net_delay.v:22:14: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... note: In instance 't'
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22 | wire[3:0] #5 val3 = cyc;
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| ^
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%Warning-STMTDLY: t/t_net_delay.v:23:14: Ignoring delay on this statement due to --no-timing
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: ... note: In instance 't'
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23 | wire[3:0] #5 val4;
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| ^
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%Warning-ASSIGNDLY: t/t_net_delay.v:24:14: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... note: In instance 't'
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24 | wire[3:0] #3 val5 = x, val6 = cyc;
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| ^
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%Warning-ASSIGNDLY: t/t_net_delay.v:27:11: Ignoring timing control on this assignment/primitive due to --no-timing
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: ... note: In instance 't'
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27 | assign #3 val2 = cyc;
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| ^
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%Warning-STMTDLY: t/t_net_delay.v:39:26: Ignoring delay on this statement due to --no-timing
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: ... note: In instance 't'
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39 | always @(posedge clk) #1 begin
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| ^
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%Error: Exiting due to
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