github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-04-05 04:02:37 +00:00
Code Issues Packages Projects Releases Wiki Activity

Support IEEE-compliant intra-assign delays (#3711) (#5441)

Browse Source
This commit is contained in:
Krzysztof Bieganski 2024-09-07 00:13:52 +02:00 committed by GitHub
parent d6923c8571
commit afb8428db4
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
14 changed files with 561 additions and 11334 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/V3AstNodeOther.h
View File

@ -3611,6 +3611,7 @@ public:
});
}
bool brokeLhsMustBeLvalue() const override { return true; }
AstDelay* getLhsNetDelay() const;
AstAlways* convertToAlways();
};

9
src/V3AstNodes.cpp
View File

@ -2899,6 +2899,15 @@ void AstCUse::dumpJson(std::ostream& str) const {
dumpJsonGen(str);
}
static AstDelay* getLhsNetDelayRecurse(const AstNodeExpr* const nodep) {
if (const AstNodeVarRef* const refp = VN_CAST(nodep, NodeVarRef)) {
if (refp->varp()->delayp()) return refp->varp()->delayp();
} else if (const AstNodeSel* const selp = VN_CAST(nodep, NodeSel)) {
return getLhsNetDelayRecurse(selp->fromp());
}
return nullptr;
}
AstDelay* AstAssignW::getLhsNetDelay() const { return getLhsNetDelayRecurse(lhsp()); }
AstAlways* AstAssignW::convertToAlways() {
const bool hasTimingControl = isTimingControl();
AstNodeExpr* const lhs1p = lhsp()->unlinkFrBack();

3
src/V3ParseGrammar.cpp
View File

@ -226,8 +226,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
nodep->ansi(m_pinAnsi);
nodep->declTyped(m_varDeclTyped);
nodep->lifetime(m_varLifetime);
nodep->delayp(m_netDelayp);
m_netDelayp = nullptr;
nodep->delayp(getNetDelay());
if (GRAMMARP->m_varDecl != VVarType::UNKNOWN) nodep->combineType(GRAMMARP->m_varDecl);
if (GRAMMARP->m_varIO != VDirection::NONE) {
nodep->declDirection(GRAMMARP->m_varIO);

10
src/V3SchedTiming.cpp
View File

@ -300,14 +300,8 @@ void transformForks(AstNetlist* const netlistp) {
// If not a fork..join, copy. All write refs should've been handled by V3Fork
bool passByValue = !m_forkp->joinType().join();
if (!varp->isFuncLocal()) {
if (VString::startsWith(varp->name(), "__Vintra")) {
// Pass it by value to the new function, as otherwise there are issues with
// -flocalize (see t_timing_intra_assign)
passByValue = true;
} else {
// Not func local. Its lifetime is longer than the forked process. Skip
return;
}
// Not func local. Its lifetime is longer than the forked process. Skip
return;
} else if (!varp->user1()) {
// Not declared before the fork. It cannot outlive the forked process
return;

177
src/V3Timing.cpp
View File

@ -445,6 +445,8 @@ class TimingControlVisitor final : public VNVisitor {
// NODE STATE
// Ast{Always,NodeCCall,Fork,NodeAssign}::user1() -> bool. Set true if the node has
// been processed.
// AstAssignW::user1() -> bool. Set true if the assignment
// represents the net delay
// AstSenTree::user1() -> AstVarScope*. Trigger scheduler assigned
// to this sentree
// Ast{NodeProcedure,CFunc,Begin}::user2() -> bool. Set true if process/task
@ -471,7 +473,9 @@ class TimingControlVisitor final : public VNVisitor {
// Unique names
V3UniqueNames m_dlyforkNames{"__Vdlyfork"}; // Names for temp AssignW vars
V3UniqueNames m_contAssignVarNames{"__VassignWtmp"}; // Names for temp AssignW vars
V3UniqueNames m_contAsgnTmpNames{"__VassignWtmp"}; // Names for temp AssignW vars
V3UniqueNames m_contAsgnGenNames{"__VassignWgen"}; // Continuous assign generation name
// generator
V3UniqueNames m_intraValueNames{"__Vintraval"}; // Intra assign delay value var names
V3UniqueNames m_intraIndexNames{"__Vintraidx"}; // Intra assign delay index var names
V3UniqueNames m_intraLsbNames{"__Vintralsb"}; // Intra assign delay LSB var names
@ -493,47 +497,24 @@ class TimingControlVisitor final : public VNVisitor {
SenExprBuilder* m_senExprBuilderp = nullptr; // Sens expression builder for current m_scope
// METHODS
// Find net delay on the LHS of an assignment
AstDelay* getLhsNetDelayRecurse(const AstNodeExpr* const nodep) const {
if (const AstNodeVarRef* const refp = VN_CAST(nodep, NodeVarRef)) {
if (refp->varp()->delayp()) return refp->varp()->delayp()->unlinkFrBack();
} else if (const AstSel* const selp = VN_CAST(nodep, Sel)) {
return getLhsNetDelayRecurse(selp->fromp());
}
return nullptr;
}
// Transform an assignment with an intra timing control into a timing control with the
// assignment under it
AstNode* factorOutTimingControl(AstNodeAssign* nodep) const {
AstNode* stmtp = nodep;
AstDelay* delayp = getLhsNetDelayRecurse(nodep->lhsp());
FileLine* const flp = nodep->fileline();
AstNode* const controlp = nodep->timingControlp();
if (controlp) {
controlp->unlinkFrBack();
if (auto* const assignDelayp = VN_CAST(controlp, Delay)) {
if (delayp) {
delayp->lhsp(new AstAdd{flp, delayp->lhsp()->unlinkFrBack(),
assignDelayp->lhsp()->unlinkFrBack()});
VL_DO_DANGLING(assignDelayp->deleteTree(), nodep);
} else {
delayp = assignDelayp;
}
}
}
if (delayp) {
stmtp->replaceWith(delayp);
if (AstDelay* const delayp = VN_CAST(controlp, Delay)) {
stmtp->replaceWith(delayp->unlinkFrBack());
delayp->addStmtsp(stmtp);
stmtp = delayp;
}
if (auto* const sensesp = VN_CAST(controlp, SenTree)) {
auto* const eventControlp = new AstEventControl{flp, sensesp, nullptr};
} else if (AstSenTree* const sensesp = VN_CAST(controlp, SenTree)) {
AstEventControl* const eventControlp
= new AstEventControl{sensesp->fileline(), sensesp->unlinkFrBack(), nullptr};
stmtp->replaceWith(eventControlp);
eventControlp->addStmtsp(stmtp);
stmtp = eventControlp;
} else if (auto* const beginp = VN_CAST(controlp, Begin)) {
} else if (AstBegin* const beginp = VN_CAST(controlp, Begin)) {
// Begin from V3AssertPre
stmtp->replaceWith(beginp);
stmtp->replaceWith(beginp->unlinkFrBack());
beginp->addStmtsp(stmtp);
stmtp = beginp;
}
@ -1062,58 +1043,106 @@ class TimingControlVisitor final : public VNVisitor {
controlp->addHereThisAsNext(
new AstAssign{flp, new AstVarRef{flp, newvscp, VAccess::WRITE}, valuep});
};
// Create the intermediate select vars. Note: because 'foreach' proceeds in
// pre-order, and we replace indices in selects with variables, we cannot
// reach another select under the index position. This is exactly what
// we want as only the top level selects are LValues. As an example,
// this transforms 'x[a[i]][b[j]] = y'
// into 't1 = a[i]; t0 = b[j]; x[t1][t0] = y'.
nodep->lhsp()->foreach([&](AstSel* selp) {
if (VN_IS(selp->lsbp(), Const)) return;
replaceWithIntermediate(selp->lsbp(), m_intraLsbNames.get(nodep));
// widthp should be const
});
nodep->lhsp()->foreach([&](AstNodeSel* selp) {
if (VN_IS(selp->bitp(), Const)) return;
replaceWithIntermediate(selp->bitp(), m_intraIndexNames.get(nodep));
});
// NBAs with delays evaluate LHS indices immediately
if (inAssignDly) {
// Create the intermediate select vars. Note: because 'foreach' proceeds in pre-order,
// and we replace indices in selects with variables, we cannot reach another select
// under the index position. This is exactly what we want as only the top level selects
// are LValues. As an example, this transforms 'x[a[i]][b[j]] = y' into 't1 = a[i]; t0
// = b[j]; x[t1][t0] = y'.
nodep->lhsp()->foreach([&](AstSel* selp) {
if (VN_IS(selp->lsbp(), Const)) return;
replaceWithIntermediate(selp->lsbp(), m_intraLsbNames.get(nodep));
// widthp should be const
});
nodep->lhsp()->foreach([&](AstNodeSel* selp) {
if (VN_IS(selp->bitp(), Const)) return;
replaceWithIntermediate(selp->bitp(), m_intraIndexNames.get(nodep));
});
}
// Replace the RHS with an intermediate value var
replaceWithIntermediate(nodep->rhsp(), m_intraValueNames.get(nodep));
}
void visit(AstAssignW* nodep) override {
AstDelay* const netDelayp = getLhsNetDelayRecurse(nodep->lhsp());
if (!netDelayp && !nodep->timingControlp()) return;
// This assignment will be converted to an always. In some cases this may generate an
// UNOPTFLAT, e.g.: assign #1 clk = ~clk. We create a temp var for the LHS of this
// assign, to disable the UNOPTFLAT warning for it.
// TODO: Find a way to do this without introducing this var. Perhaps make
// V3SchedAcyclic recognize awaits and prevent it from treating this kind of logic as
// cyclic
AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
std::string varname;
if (auto* const refp = VN_CAST(lhsp, VarRef)) {
varname = m_contAssignVarNames.get(refp->name());
} else {
varname = m_contAssignVarNames.get(lhsp);
}
auto* const tempvscp = m_scopep->createTemp(varname, lhsp->dtypep());
tempvscp->varp()->delayp(netDelayp);
FileLine* const flp = nodep->fileline();
// Get the net delay unless this assignment was created for handling the net delay (user1)
AstDelay* const netDelayp = nodep->user1() ? nullptr : nodep->getLhsNetDelay();
if (netDelayp) {
if (nodep->timingControlp()) {
// If this assignment has a delay, create another one to handle the net delay
AstVarScope* const newvscp
= createTemp(flp, m_contAsgnTmpNames.get(nodep), nodep->dtypep());
AstAssignW* assignp = new AstAssignW{
nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
new AstVarRef{flp, newvscp, VAccess::READ}, netDelayp->cloneTree(false)};
assignp->user1(true);
nodep->addNextHere(assignp);
nodep->lhsp(new AstVarRef{flp, newvscp, VAccess::WRITE});
} else {
// Else just use this one with the net delay
nodep->timingControlp(netDelayp->cloneTree(false));
}
}
if (!nodep->timingControlp()) return;
// There will be some circular logic here, suppress the warning for newly created vars
flp->modifyWarnOff(V3ErrorCode::UNOPTFLAT, true);
tempvscp->fileline(flp);
tempvscp->varp()->fileline(flp);
// Remap the LHS to the new temp var
nodep->lhsp(new AstVarRef{flp, tempvscp, VAccess::WRITE});
// Also suppress the warning for the LHS var, for cases like `assign #1 clk = ~clk;`
// TODO: Restore the warning for other, non-delayed drivers
nodep->lhsp()->foreach([](AstVarRef* refp) {
if (refp->access().isWriteOrRW()) {
refp->varp()->fileline()->modifyWarnOff(V3ErrorCode::UNOPTFLAT, true);
}
});
// Convert it to an always; the new assign with intra delay will be handled by
// visit(AstNodeAssign*)
AstAlways* const alwaysp = nodep->convertToAlways();
visit(alwaysp);
// Put the LHS back in the AssignW; put the temp var on the RHS
nodep->lhsp(lhsp);
nodep->rhsp(new AstVarRef{flp, tempvscp, VAccess::READ});
// Put the AssignW right after the always. Different order can produce UNOPTFLAT on the LHS
// var
alwaysp->addNextHere(nodep);
visit(alwaysp); // Visit now as we need to do some post-processing
VL_DO_DANGLING(nodep->deleteTree(), nodep);
// IEEE 1800-2023 10.3.3 - if the RHS value differs from the currently scheduled value to
// be assigned, the currently scheduled assignment is descheduled. To keep track if an
// assignment should be descheduled, each scheduled assignment event has a 'generation',
// and if at assignment time its generation differs from the current generation, it won't
// be performed
AstFork* const forkp = VN_AS(alwaysp->stmtsp(), Fork);
UASSERT_OBJ(forkp, alwaysp, "Fork should be there from convertToAlways()");
AstBegin* const beginp = VN_AS(forkp->stmtsp(), Begin);
UASSERT_OBJ(beginp, alwaysp, "Begin should be there from convertToAlways()");
AstAssign* const preAssignp = VN_AS(beginp->stmtsp(), Assign);
UASSERT_OBJ(preAssignp, alwaysp, "Pre-assign should be there from convertToAlways()");
AstAssign* const postAssignp = VN_AS(preAssignp->nextp()->nextp(), Assign);
UASSERT_OBJ(postAssignp, alwaysp, "Post-assign should be there from convertToAlways()");
// Increment generation and copy it to a local
AstVarScope* const generationVarp
= createTemp(flp, m_contAsgnGenNames.get(alwaysp), alwaysp->findUInt64DType());
AstVarScope* const genLocalVarp
= createTemp(flp, generationVarp->varp()->name() + "__local",
alwaysp->findUInt64DType(), preAssignp);
preAssignp->addHereThisAsNext(
new AstAssign{flp, new AstVarRef{flp, generationVarp, VAccess::WRITE},
new AstAdd{flp, new AstVarRef{flp, generationVarp, VAccess::READ},
new AstConst{flp, 1}}});
preAssignp->addHereThisAsNext(
new AstAssign{flp, new AstVarRef{flp, genLocalVarp, VAccess::WRITE},
new AstVarRef{flp, generationVarp, VAccess::READ}});
// If the current generation is same as the one saved in the local var, assign
beginp->addStmtsp(
new AstIf{flp,
new AstEq{flp, new AstVarRef{flp, generationVarp, VAccess::READ},
new AstVarRef{flp, genLocalVarp, VAccess::READ}},
postAssignp->unlinkFrBack()});
// Save scheduled RHS value before delay
AstVarScope* const tmpVarp
= createTemp(flp, m_contAsgnTmpNames.get(alwaysp), preAssignp->rhsp()->dtypep());
AstVarRef* const tmpAssignRhsp = VN_AS(preAssignp->lhsp(), VarRef)->cloneTree(false);
tmpAssignRhsp->access(VAccess::WRITE);
preAssignp->addNextHere(
new AstAssign{flp, new AstVarRef{flp, tmpVarp, VAccess::WRITE}, tmpAssignRhsp});
// If the RHS is different from the currently scheduled value, schedule the new assignment
// The generation will increase, effectively 'descheduling' the previous assignment.
alwaysp->addStmtsp(new AstIf{flp,
new AstNeq{flp, preAssignp->rhsp()->cloneTree(false),
new AstVarRef{flp, tmpVarp, VAccess::READ}},
forkp->unlinkFrBack()});
}
void visit(AstDisableFork* nodep) override {
if (hasFlags(m_procp, T_HAS_PROC)) return;

5
src/V3Tristate.cpp
View File

@ -1247,7 +1247,10 @@ class TristateVisitor final : public TristateBaseVisitor {
VL_RESTORER(m_alhs);
VL_RESTORER(m_currentStrength);
if (m_graphing) {
if (AstAssignW* assignWp = VN_CAST(nodep, AssignW)) addToAssignmentList(assignWp);
if (AstAssignW* assignWp = VN_CAST(nodep, AssignW)) {
if (assignWp->timingControlp() || assignWp->getLhsNetDelay()) return;
addToAssignmentList(assignWp);
}
if (nodep->user2() & U2_GRAPHING) return;
VL_RESTORER(m_logicp);

12
src/verilog.y
View File

@ -83,7 +83,8 @@ public:
AstCase* m_caseAttrp = nullptr; // Current case statement for attribute adding
AstNodeDType* m_varDTypep = nullptr; // Pointer to data type for next signal declaration
AstNodeDType* m_memDTypep = nullptr; // Pointer to data type for next member declaration
AstDelay* m_netDelayp = nullptr; // Pointer to delay for next signal declaration
std::unique_ptr<AstDelay> m_netDelayp = nullptr; // Pointer to delay for next signal
// declaration
AstStrengthSpec* m_netStrengthp = nullptr; // Pointer to strength for next net declaration
FileLine* m_instModuleFl = nullptr; // Fileline of module referenced for instantiations
AstPin* m_instParamp = nullptr; // Parameters for instantiations
@ -211,7 +212,8 @@ public:
if (m_varDTypep) VL_DO_CLEAR(m_varDTypep->deleteTree(), m_varDTypep = nullptr);
m_varDTypep = dtypep;
}
void setNetDelay(AstDelay* netDelayp) { m_netDelayp = netDelayp; }
void setNetDelay(AstDelay* netDelayp) { m_netDelayp.reset(netDelayp); }
AstDelay* getNetDelay() { return m_netDelayp.release(); }
void setNetStrength(AstStrengthSpec* netStrengthp) { m_netStrengthp = netStrengthp; }
void pinPush() {
m_pinStack.push(m_pinNum);
@ -3045,8 +3047,10 @@ netSig<varp>: // IEEE: net_decl_assignment - one element from
netId sigAttrListE
{ $$ = VARDONEA($<fl>1, *$1, nullptr, $2); }
| netId sigAttrListE '=' expr
{ $$ = VARDONEA($<fl>1, *$1, nullptr, $2);
auto* const assignp = new AstAssignW{$3, new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1}, $4};
{ AstDelay* const delayp = GRAMMARP->getNetDelay();
AstAssignW* const assignp = new AstAssignW{$3, new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1}, $4, delayp};
$$ = VARDONEA($<fl>1, *$1, nullptr, $2);
if (delayp) GRAMMARP->setNetDelay(delayp->cloneTree(false));
if (GRAMMARP->m_netStrengthp) assignp->strengthSpecp(GRAMMARP->m_netStrengthp->cloneTree(false));
AstNode::addNext<AstNode, AstNode>($$, assignp); }
| netId variable_dimensionList sigAttrListE

34
test_regress/t/t_net_delay.out
View File

@ -1,15 +1,35 @@
%Warning-STMTDLY: t/t_net_delay.v:16:14: Ignoring delay on this statement due to --no-timing
%Warning-STMTDLY: t/t_net_delay.v:14:11: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
16 | wire[3:0] #4 val1 = half_cyc;
| ^
14 | always #2 clk = ~clk;
| ^
... For warning description see https://verilator.org/warn/STMTDLY?v=latest
... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
%Warning-STMTDLY: t/t_net_delay.v:17:14: Ignoring delay on this statement due to --no-timing
%Warning-STMTDLY: t/t_net_delay.v:20:14: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
17 | wire[3:0] #4 val2;
20 | wire[3:0] #3 val1;
| ^
%Warning-ASSIGNDLY: t/t_net_delay.v:20:11: Ignoring timing control on this assignment/primitive due to --no-timing
%Warning-STMTDLY: t/t_net_delay.v:21:14: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
21 | wire[3:0] #3 val2;
| ^
%Warning-ASSIGNDLY: t/t_net_delay.v:22:14: Ignoring timing control on this assignment/primitive due to --no-timing
: ... note: In instance 't'
20 | assign #4 val2 = half_cyc;
22 | wire[3:0] #5 val3 = cyc;
| ^
%Warning-STMTDLY: t/t_net_delay.v:23:14: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
23 | wire[3:0] #5 val4;
| ^
%Warning-ASSIGNDLY: t/t_net_delay.v:24:14: Ignoring timing control on this assignment/primitive due to --no-timing
: ... note: In instance 't'
24 | wire[3:0] #3 val5 = x, val6 = cyc;
| ^
%Warning-ASSIGNDLY: t/t_net_delay.v:27:11: Ignoring timing control on this assignment/primitive due to --no-timing
: ... note: In instance 't'
27 | assign #3 val2 = cyc;
| ^
%Warning-STMTDLY: t/t_net_delay.v:39:26: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
39 | always @(posedge clk) #1 begin
| ^
%Error: Exiting due to

55
test_regress/t/t_net_delay.v
View File

@ -7,30 +7,47 @@
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t;
// verilator lint_off UNOPTFLAT
logic clk = 0;
// verilator lint_on UNOPTFLAT
always #2 clk = ~clk;
wire[3:0] #4 val1 = half_cyc;
wire[3:0] #4 val2;
reg[3:0] half_cyc = 0;
// verilator lint_off UNDRIVEN
wire[3:0] x;
// verilator lint_on UNDRIVEN
reg[3:0] cyc = 0;
wire[3:0] #3 val1;
wire[3:0] #3 val2;
wire[3:0] #5 val3 = cyc;
wire[3:0] #5 val4;
wire[3:0] #3 val5 = x, val6 = cyc;
assign #4 val2 = half_cyc;
assign val1 = cyc;
assign #3 val2 = cyc;
assign val4 = cyc;
assign val5 = cyc;
always @(clk) begin
if ($time > 0) half_cyc <= half_cyc + 1;
`ifdef TEST_VERBOSE
$strobe("[%0t] half_cyc=%0d, val1=%0d, val2=%0d", $time, half_cyc, val1, val2);
`endif
if (half_cyc >= 7) begin
`checkh(val1, half_cyc - 3);
`checkh(val2, half_cyc - 7);
end
if (half_cyc == 15) begin
always @(posedge clk) begin
if ($time > 0) cyc <= cyc + 1;
if (cyc == 15) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) #1 begin
`ifdef TEST_VERBOSE
$display("[%0t] cyc=%0d val1=%0d val2=%0d val3=%0d val4=%0d val5=%0d val6=%0d",
$time, cyc, val1, val2, val3, val4, val5, val6);
`endif
if (cyc >= 3) begin
`checkh(val1, cyc - 1);
`checkh(val2, cyc - 2);
`checkh(val3, 0);
`checkh(val4, 0);
`checkh(val5, cyc);
`checkh(val6, cyc - 1);
end
end
endmodule

510
test_regress/t/t_timing_debug1.out
View File

File diff suppressed because it is too large Load Diff

38
test_regress/t/t_timing_intra_assign.out
View File

@ -1,15 +1,25 @@
val[0]=0 val[1]=0 val[2]=0
val[0]=1 val[1]=0 val[2]=0
val[0]=2 val[1]=0 val[2]=15
val[0]=3 val[1]=0 val[2]=15
val[0]=4 val[1]=1 val[2]=14
val[0]=5 val[1]=1 val[2]=14
val[0]=6 val[1]=2 val[2]=13
val[0]=7 val[1]=4 val[2]=11
val[0]=8 val[1]=7 val[2]=8
val[0]=9 val[1]=7 val[2]=8
val[0]=10 val[1]=7 val[2]=8
val[0]=11 val[1]=7 val[2]=8
val[0]=12 val[1]=7 val[2]=8
val[0]=13 val[1]=7 val[2]=8
[0] val[0]=0 val[1]=0 val[2]=0 net[0]=0 net[1]=0
[10] val[0]=1 val[1]=0 val[2]=0 net[0]=0 net[1]=15
[14] val[0]=1 val[1]=1 val[2]=0 net[0]=0 net[1]=15
[16] val[0]=1 val[1]=1 val[2]=1 net[0]=0 net[1]=15
[20] val[0]=2 val[1]=1 val[2]=1 net[0]=1 net[1]=14
[24] val[0]=2 val[1]=2 val[2]=1 net[0]=1 net[1]=14
[25] val[0]=3 val[1]=2 val[2]=1 net[0]=1 net[1]=14
[29] val[0]=3 val[1]=3 val[2]=1 net[0]=2 net[1]=13
[30] val[0]=4 val[1]=3 val[2]=1 net[0]=2 net[1]=13
[34] val[0]=4 val[1]=4 val[2]=1 net[0]=3 net[1]=12
[35] val[0]=5 val[1]=4 val[2]=1 net[0]=3 net[1]=12
[39] val[0]=5 val[1]=5 val[2]=1 net[0]=4 net[1]=11
[40] val[0]=6 val[1]=5 val[2]=1 net[0]=4 net[1]=11
[44] val[0]=6 val[1]=6 val[2]=1 net[0]=5 net[1]=10
[46] val[0]=6 val[1]=6 val[2]=6 net[0]=5 net[1]=10
[50] val[0]=7 val[1]=6 val[2]=6 net[0]=6 net[1]=9
[54] val[0]=7 val[1]=7 val[2]=6 net[0]=6 net[1]=9
[56] val[0]=7 val[1]=7 val[2]=7 net[0]=6 net[1]=9
[75] val[0]=8 val[1]=7 val[2]=7 net[0]=7 net[1]=8
[76] val[0]=9 val[1]=7 val[2]=7 net[0]=7 net[1]=8
[78] val[0]=10 val[1]=7 val[2]=7 net[0]=7 net[1]=8
[79] val[0]=11 val[1]=7 val[2]=7 net[0]=7 net[1]=8
[80] val[0]=12 val[1]=7 val[2]=7 net[0]=7 net[1]=8
[82] val[0]=13 val[1]=7 val[2]=7 net[0]=7 net[1]=8
*-* All Finished *-*

4
test_regress/t/t_timing_intra_assign.pl
View File

@ -11,7 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(simulator => 1);
compile(
verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT"],
verilator_flags2 => ["--binary"],
);
execute(
@ -19,7 +19,7 @@ execute(
);
compile(
verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT -fno-localize"],
verilator_flags2 => ["--binary -fno-localize"],
);
execute(

19
test_regress/t/t_timing_intra_assign.v
View File

@ -6,28 +6,35 @@
module t;
logic[3:0] val[3];
wire[3:0] #5 net[2];
logic[1:0] idx1 = 0;
logic[1:0] idx2 = 0;
logic[0:0] idx3 = 0;
event e;
always @val[0] $write("val[0]=%0d val[1]=%0d val[2]=%0d\n", val[0], val[1], val[2]);
always @val $write("[%0t] val[0]=%0d val[1]=%0d val[2]=%0d net[0]=%0d net[1]=%0d\n",
$time, val[0], val[1], val[2], net[0], net[1]);
assign #10 {val[1], val[2]} = {val[0], 4'hf-val[0]};
assign {net[0], net[1]} = {val[1], 4'hf-val[1]};
assign #4 val[1] = val[0];
assign #6 val[2] = val[0];
always #10 begin // always so we can use NBA
val[0] = 1;
#10 val[0] = 2;
fork #5 val[0] = 3; join_none
val[0] = #10 val[0] + 2;
val[idx1] <= #10 val[idx1] + 2;
val[0] <= #10 val[idx1] + 2;
fork begin #5
val[0] = 5;
idx1 = 2;
idx2 = 3;
idx3 = 1;
idx1 = 0;
idx2 = 0;
idx3 = 0;
#40 ->e;
end join_none
idx1 = 2;
idx2 = 3;
idx3 = 1;
val[idx1][idx2[idx3+:2]] = #20 1;
@e val[0] = 8;
fork begin

11018
test_regress/t/t_timing_osc.out
View File

File diff suppressed because it is too large Load Diff