mirror of
https://github.com/verilator/verilator.git
synced 2025-01-09 16:17:36 +00:00
16 lines
416 B
Verilog
16 lines
416 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2012 by Wilson Snyder.
|
|
|
|
module t (/*AUTOARG*/);
|
|
wire ok = 1'b0;
|
|
// verilator lint_off PINNOCONNECT
|
|
sub sub (.ok(ok), .nc());
|
|
// verilator lint_on PINNOCONNECT
|
|
endmodule
|
|
|
|
module sub (input ok, input nc);
|
|
initial if (ok&&nc) begin end // No unused warning
|
|
endmodule
|