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33 lines
701 B
Systemverilog
33 lines
701 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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event e;
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initial begin
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int x;
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#1
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fork @e; @e; join;
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@e
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wait(x == 4)
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x = #1 8;
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if (x != 8) $stop;
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if ($time != 0) $stop;
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@e
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if (!e.triggered) $stop;
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if ($time != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial #1 ->e;
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initial #2 $stop; // timeout
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endmodule
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`ifdef VERILATOR_TIMING
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`error "VERILATOR_TIMING should not be defined with --no-timing"
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`endif
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