Add VERILATOR_TIMING define (#3684)

docs/guide/extensions.rst

@@ -151,6 +151,13 @@ or "`ifdef`"'s may break other tools.
    Take remaining text up to the next :option:`\`verilog` mode switch and
    treat it as Verilator configuration commands.  See :ref:`Configuration Files`.
 
+.. option:: `VERILATOR_TIMING
+
+   The VERILATOR_TIMING define is set when :vlopt:`--timing` is used to
+   allow an "\`ifdef" of code dependent on this feature.  Note this define
+   is not affected by the :option:`timing_off` configuration file option
+   nor timing metacomments.
+
 .. option:: `verilog
 
    Switch back to processing Verilog code after a

src/V3Options.cpp

@@ -833,6 +833,9 @@ void V3Options::notify() {
     if (!m_dumpLevel.count("tree") && m_dumpLevel.count("tree-dot")) {
         m_dumpLevel["tree"] = m_dumpLevel["tree-dot"];
     }
+
+    // Preprocessor defines based on options used
+    if (timing().isSetTrue()) V3PreShell::defineCmdLine("VERILATOR_TIMING", "1");
 }
 
 //######################################################################

test_regress/t/t_notiming.v

@@ -26,3 +26,7 @@ module t;
    initial #1 ->e;
    initial #2 $stop; // timeout
 endmodule
+
+`ifdef VERILATOR_TIMING
+`error "VERILATOR_TIMING should not be defined with --no-timing"
+`endif

test_regress/t/t_timing_events.v

@@ -30,3 +30,7 @@ module t;
 
    initial #21 $stop; // timeout
 endmodule
+
+`ifndef VERILATOR_TIMING
+`error "VERILATOR_TIMING should have been defined as have --timing"
+`endif