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82 lines
2.1 KiB
Verilog
82 lines
2.1 KiB
Verilog
// DESCRIPTION: Verilator Test: Top level testbench for VCS or other fully Verilog compliant simulators
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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`timescale 1 ns / 1ns
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module bench;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [39:0] out_quad; // From top of top.v
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wire [1:0] out_small; // From top of top.v
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wire [69:0] out_wide; // From top of top.v
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wire passed; // From top of top.v
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// End of automatics
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reg clk;
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reg fastclk;
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reg reset_l;
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reg [1:0] in_small;
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reg [39:0] in_quad;
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reg [69:0] in_wide;
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// Test cases
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top top (/*AUTOINST*/
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// Outputs
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.passed (passed),
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.out_small (out_small[1:0]),
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.out_quad (out_quad[39:0]),
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.out_wide (out_wide[69:0]),
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// Inputs
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.clk (clk),
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.fastclk (fastclk),
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.reset_l (reset_l),
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.in_small (in_small[1:0]),
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.in_quad (in_quad[39:0]),
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.in_wide (in_wide[69:0]));
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//surefire lint_off STMINI
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//surefire lint_off STMFVR
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//surefire lint_off DLYONE
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integer fh;
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// surefire lint_off CWECBB
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initial begin
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reset_l = 1'b1; // Want to catch negedge
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fastclk = 0;
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clk = 0;
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forever begin
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in_small = 0;
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in_wide = 0;
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$write("[%0t] %x %x %x %x %x\n", $time, clk, reset_l, passed, out_small, out_wide);
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if (($time % 10) == 3) clk = 1'b1;
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if (($time % 10) == 8) clk = 1'b0;
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if ($time>10) reset_l = 1'b1;
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else if ($time > 1) reset_l = 1'b0;
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if ($time>60 || passed === 1'b1) begin
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if (passed !== 1'b1) begin
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$write("A Test failed!!!\n");
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$stop;
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end
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else begin
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$write("*-* All Finished *-*\n"); // Magic if using perl's Log::Detect
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fh = $fopen("test_passed.log");
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$fclose(fh);
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end
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$finish;
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end
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#1;
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fastclk = !fastclk;
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end
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end
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../test_v")
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// compile-command: "vlint --brief -f ../test_v/input.vc bench.v"
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// End:
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