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41 lines
885 B
Verilog
41 lines
885 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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`timescale 1 ns/ 1ns
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module top (/*AUTOARG*/
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// Outputs
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passed, out_small, out_quad, out_wide,
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// Inputs
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clk, fastclk, reset_l, in_small, in_quad, in_wide
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);
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output passed;
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input clk;
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input fastclk;
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input reset_l;
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output [1:0] out_small;
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output [39:0] out_quad;
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output [69:0] out_wide;
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input [1:0] in_small;
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input [39:0] in_quad;
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input [69:0] in_wide;
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wire [1:0] out_small = in_small | {2{reset_l}};
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wire [39:0] out_quad = in_quad | {40{reset_l}};
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wire [69:0] out_wide = in_wide | {70{reset_l}};
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// Test cases
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t t (/*AUTOINST*/
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// Outputs
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.passed (passed),
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// Inputs
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.clk (clk),
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.fastclk (fastclk),
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.reset_l (reset_l));
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endmodule
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