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115 lines
2.9 KiB
Verilog
115 lines
2.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t_clk (/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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fastclk, clk, reset_l
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);
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input fastclk;
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input clk;
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input reset_l;
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output passed; reg passed; initial passed = 0;
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// surefire lint_off STMINI
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// surefire lint_off CWECSB
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// surefire lint_off NBAJAM
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reg _ranit; initial _ranit=0;
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// surefire lint_off UDDSMX
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reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
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wire [7:0] clk_clocks_d1r;
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wire [7:0] clk_clocks_d1sr;
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wire [7:0] clk_clocks_cp2_d1r;
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wire [7:0] clk_clocks_cp2_d1sr;
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// verilator lint_off MULTIDRIVEN
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reg [7:0] int_clocks; initial int_clocks = 0;
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// verilator lint_on MULTIDRIVEN
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reg [7:0] int_clocks_copy;
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// verilator lint_off GENCLK
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reg internal_clk; initial internal_clk = 0;
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reg reset_int_;
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// verilator lint_on GENCLK
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always @ (posedge clk) begin
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//$write("CLK1 %x\n", reset_l);
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if (!reset_l) begin
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clk_clocks <= 0;
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int_clocks <= 0;
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internal_clk <= 1'b1;
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reset_int_ <= 0;
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end
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else begin
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internal_clk <= ~internal_clk;
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if (!_ranit) begin
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_ranit <= 1;
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$write("[%0t] t_clk: Running\n",$time);
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reset_int_ <= 1;
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end
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end
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end
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reg [7:0] sig_rst;
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always @ (posedge clk or negedge reset_l) begin
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//$write("CLK2 %x sr=%x\n", reset_l, sig_rst);
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if (!reset_l) begin
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sig_rst <= 0;
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end
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else begin
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sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
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end
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end
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always @ (posedge clk) begin
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//$write("CLK3 %x cc=%x sr=%x\n", reset_l, clk_clocks, sig_rst);
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if (!reset_l) begin
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clk_clocks <= 0;
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end
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else begin
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clk_clocks <= clk_clocks + 8'd1;
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if (clk_clocks == 4) begin
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if (sig_rst !== 4) $stop;
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if (clk_clocks_d1r !== 3) $stop;
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if (int_clocks !== 2) $stop;
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if (int_clocks_copy !== 2) $stop;
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if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
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if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
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passed <= 1'b1;
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$write("[%0t] t_clk: Passed\n",$time);
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end
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end
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end
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reg [7:0] resetted;
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always @ (posedge clk or negedge reset_int_) begin
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//$write("CLK4 %x\n", reset_l);
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if (!reset_int_) begin
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resetted <= 0;
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end
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else begin
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resetted <= resetted + 8'd1;
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end
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end
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always @ (int_clocks) begin
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int_clocks_copy = int_clocks;
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end
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always @ (negedge internal_clk) begin
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int_clocks <= int_clocks + 8'd1;
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end
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t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
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.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
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t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
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.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
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t_clk_two two (/*AUTOINST*/
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// Inputs
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.fastclk (fastclk),
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.reset_l (reset_l));
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endmodule
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