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39 lines
1.1 KiB
Verilog
39 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t;
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integer p_i;
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reg [7*8:1] p_str;
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initial begin
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if ($test$plusargs("PLUS")!==1) $stop;
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if ($test$plusargs("PLUSNOT")!==0) $stop;
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if ($test$plusargs("PL")!==1) $stop;
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//if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer
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if ($test$plusargs("NOTTHERE")!==0) $stop;
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p_i = 10;
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if ($value$plusargs("NOTTHERE%d", p_i)!==0) $stop;
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if (p_i !== 10) $stop;
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if ($value$plusargs("INT=%d", p_i)!==1) $stop;
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if (p_i !== 32'd1234) $stop;
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if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also
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if (p_i !== 32'h1234) $stop;
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if ($value$plusargs("INT=%o", p_i)!==1) $stop;
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if (p_i !== 32'o1234) $stop;
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if ($value$plusargs("IN%s", p_str)!==1) $stop;
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$display("str='%s'",p_str);
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if (p_str !== "T=1234") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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