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69 lines
1.5 KiB
Verilog
69 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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package defs;
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function automatic integer max;
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input integer a;
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input integer b;
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max = (a > b) ? a : b;
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endfunction
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function automatic integer log2;
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input integer value;
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value = value >> 1;
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for (log2 = 0; value > 0; log2 = log2 + 1)
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value = value >> 1;
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endfunction
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function automatic integer ceil_log2;
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input integer value;
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value = value - 1;
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for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
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value = value >> 1;
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endfunction
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endpackage
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module sub();
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import defs::*;
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parameter RAND_NUM_MAX = "";
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localparam DATA_RANGE = RAND_NUM_MAX + 1;
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localparam DATA_WIDTH = ceil_log2(DATA_RANGE);
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localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1));
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endmodule
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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import defs::*;
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parameter WHICH = 0;
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parameter MAX_COUNT = 10;
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localparam MAX_EXPONENT = log2(MAX_COUNT);
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localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1);
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input clk;
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generate
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if (WHICH == 1)
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begin : which_true
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sub sub_true();
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defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT;
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end
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else
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begin : which_false
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sub sub_false();
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defparam sub_false.RAND_NUM_MAX = MAX_COUNT;
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end
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endgenerate
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endmodule
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