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54 lines
1.2 KiB
Verilog
54 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [7:0] cyc; initial cyc=0;
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reg [31:0] loops;
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reg [31:0] loops2;
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always @ (posedge clk) begin
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cyc <= cyc+8'd1;
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if (cyc == 8'd1) begin
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$write("[%0t] t_loop: Running\n",$time);
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// Unwind <
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loops = 0;
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loops2 = 0;
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for (int i=0; i<16; i=i+1) begin
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loops = loops + i; // surefire lint_off_line ASWEMB
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loops2 = loops2 + i; // surefire lint_off_line ASWEMB
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end
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if (loops !== 120) $stop;
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if (loops2 !== 120) $stop;
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// Check we can declare the same signal twice
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loops = 0;
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for (int i=0; i<=16; i=i+1) begin
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loops = loops + 1;
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end
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if (loops !== 17) $stop;
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// Check type is correct
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loops = 0;
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for (byte unsigned i=5; i>4; i=i+1) begin
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loops = loops + 1;
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end
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if (loops !== 251) $stop;
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// Check large loops
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loops = 0;
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for (int i=0; i<100000; i=i+1) begin
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loops = loops + 1;
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end
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if (loops !== 100000) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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