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20 lines
409 B
Verilog
20 lines
409 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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covlabel:
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cover property (@(posedge clk) cyc==5);
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covlabel: // Error: Duplicate block_identifier
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cover property (@(posedge clk) cyc==5);
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endmodule
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