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- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
40 lines
967 B
Verilog
40 lines
967 B
Verilog
// -*- Verilog -*-
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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//====================================================================
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// Module gray2bin
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// convert an arbitrary width gray coded number to binary. The conversion
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// of a 4 bit gray (represented as "g") to binary ("b") would go as follows:
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// b[3] = ^g[3] = g[3]
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// b[2] = ^g[3:2]
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// b[1] = ^g[3:1]
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// b[0] = ^g[3:[SZ-1:0] cur0]
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module t_func_grey2bin (/*AUTOARG*/
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// Outputs
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b,
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// Inputs
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g
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);
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// surefire lint_off STMFOR
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parameter SZ = 5;
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output [SZ-1:0] b;
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input [SZ-1:0] g;
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [SZ-1:0] b;
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// End of automatics
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integer i;
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always @(/*AUTOSENSE*/g)
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for (i=0; i<SZ; i=i+1)
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b[i] = ^(g >> i); // surefire lint_off_line LATASS
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endmodule
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