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59 lines
1.0 KiB
Verilog
59 lines
1.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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parameter PAR = 3;
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m1 #(PAR) m1();
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m3 #(PAR) m3();
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input clk;
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integer cyc=1;
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reg [4:0] bitsel;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==0) begin
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bitsel = 0;
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if (PAR[bitsel]!==1'b1) $stop;
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bitsel = 1;
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if (PAR[bitsel]!==1'b1) $stop;
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bitsel = 2;
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if (PAR[bitsel]!==1'b0) $stop;
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end
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if (cyc==1) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module m1;
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parameter PAR1 = 0;
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m2 #(PAR1-1) m2 ();
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endmodule
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module m2;
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parameter PAR2 = 10;
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initial begin
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$display("%x",PAR2);
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if (PAR2 !== 2) $stop;
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end
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endmodule
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module m3;
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localparam LOC = 13;
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parameter PAR = 10;
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initial begin
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$display("%x %x",LOC,PAR);
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if (LOC !== 13) $stop;
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if (PAR !== 3) $stop;
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end
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endmodule
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