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1c1b95161b
* Add a test to make sure that lib modules (loaded via -y option) can be a hier_block. * Add HDL file of the hier_block to the source list if the module is loaded via -y option. (Each hier_block is treated as a top module when processing the hier_block.) * Use "\n" for delimiter as the other files
15 lines
320 B
Systemverilog
15 lines
320 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Yutetsu TAKATSUKASA
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module t;
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t_flag_relinc_sub i_t_flag_relinc_sub();
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endmodule
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`ifdef VERILATOR
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`verilator_config
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hier_block -module "t_flag_relinc_sub"
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`verilog
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`endif
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